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How can I verify if the syntax of sdc constraints is correct before starting compilation?
I tried to execute sdc constraint from tcl console in the gui but got an error that sdc commands are part of quartus_sta, quartus_fit package.
I tried different methods to include these packages:
- quartus_sdc::create_clock -name {name} ...
- quartus_sta::create_clock -name{name}...
But I am not able to load these packages as fitter step is not done. However I want to verify that my commands have right syntax before fitter starts.
Even after the fitter step, if fitter fails, I am not able to execute sdc commands in the tcl to verify syntax.
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Hi,
I don't usually use tcl console on Quartus GUI, instead you can try using tcl console on Timing Analyzer GUI and use the help option.
For example you want to check for create_clock syntax, just enter "create_clock -help" and it will show how to use the correct syntax.
Unfortunately I don't think you can check if your sdc command in particular is correct if you have added all the clock names and targets etc. (if this was what you were trying to do) because you don't have the timing netlist so it will always say that it cannot find those targets.
Regards,
Nurina
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
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Hi,
Just found a different way which I think you might like-
On Quartus GUI, create a new sdc file. On the editor you can right click and select "Insert Constraint" and this would guide you to correctly write an SDC constraint.
Regards,
Nurina
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
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I tried to run sdc from timing analyzer gui (after fitter step was complete)
but i get this error for any command.
what am i doing wrong here? is the command incorrect?
what is the meaning of this error message? A useful error message would be helpful but this not say anything about the error.
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Hi,
I'm not exactly sure what it means. I don't see any mistakes in that.
Since you have run fitter, I would save all the SDC constraints in an SDC file, then run it on Timing Analyzer. Steps available here: https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/step-4-run-timing-analysis.html
Then after you have run timing analysis, I suggest to report ignored constraints, this would report the constraints that are ignored possibly due to wrong syntax, or missing targets. So from here you have a clue of which constraints you should fix.
Regards,
Nurina
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
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Hi,
Any updates?
Regards,
Nurina
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Hi,
We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
If any answer from the community or Intel Support are helpful, feel free to rank your support experience by rating 4/5 survey. Please let me know of any inconvenience so that I may improve your future service experience.
Have a great day!
Best regards,
Nurina W.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

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