I've downloaded the altpciechdma.c driver for the Altera Arria GX dev kit.
The char part of it is not yet finished (due to the comments). And a module is missign "mapper_user_to_sg.h". Smb has tried to finish this part of the driver by himself? Or maybe I've missed the "mapper_user_to_sg.h" module? I need to talk to the driver from userspace. (Using LInux 2.6.25)链接已复制
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Anyone figured this out?
I spent a few days trying to get to this point. The DMA test works fine now, but I'd like to register the character device and I am missing that mapper_user_to_sg.h file. I can't seem to find it anywhere on google, I wonder if it's just a placeholder or if the file actually exists somewhere... If anyone managed to solve this issue help would be much appreciated. Thank you!Thanks for the reply!
I get this kind of errors when commenting the include file: error: dereferencing pointer to incomplete type error: implicit declaration of function ‘sg_create_mapper’ error: implicit declaration of function ‘sg_destroy_mapper’ error: implicit declaration of function ‘sgm_map_user_pages’ error: implicit declaration of function ‘sgm_unmap_user_pages’ error: variable ‘sg_fops’ has initializer but incomplete type error: unknown field ‘owner’ specified in initializer error: unknown field ‘open’ specified in initializer error: unknown field ‘release’ specified in initializer error: unknown field ‘write’ specified in initializer error: implicit declaration of function ‘alloc_chrdev_region’ error: implicit declaration of function ‘unregister_chrdev_region’ After further googling I found this code: svn.assembla.com/svn/altpciechdma/user_dma_sg.c It has some of the missing functions in it. With some approximate copy/pasting I can get the driver to compile and the char device functionalities to (apparently) work. Thank you :).Hi everyone.
I've been trying to get the 'DMA test' working for some time now, but without any success. Nevertheless, the 'probe()' function works well. Would anyone kindly provide some ideas of what may I be overlooking? Best regards.Hi Igor.
Thanks for you reply. Here goes the dmesg output: [ 332.548209] altpciechdma exit(), built at Jan 4 2012 11:49:31 [ 339.762209] altpciechdma init(), built at Dec 31 2007 19:54:16 [ 339.762273] probe(dev = 0xf7025800, pciid = 0xf8262cc0) [ 339.762283] probe() ape = 0xef8826c0 [ 339.762290] sizeof(struct ape_chdma_table) = 4096. [ 339.762306] table_virt = ee50a000, table_bus = 0x 2e50a000. [ 339.762336] altpciechdma 0000:01:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 339.762360] altpciechdma 0000:01:00.0: setting latency timer to 64 [ 339.762454] altpciechdma 0000:01:00.0: irq 28 for MSI/MSI-X [ 339.762478] Enabled MSI interrupting. [ 339.762581] Using a 64-bit DMA mask. [ 339.762595] IRQ pin# 1 (0=none, 1=INTA#...4=INTD#). [ 339.762605] IRQ line# 11. [ 339.762650] Succesfully requested IRQ# 28 with dev_id 0xef8826c0 [ 339.762661] BAR0 0xd2100000-0xd2100fff flags 0x0012120c [ 339.762669] BAR2 0xfe500000-0xfe507fff flags 0x00020200 [ 339.762727] BAR[0] mapped at 0xf827a000 with length 4096(/4096). [ 339.762759] BAR[2] mapped at 0xf827e000 with length 256(/32768). [ 339.762768] bar_tests(), PAGE_SIZE = 0x1000 [ 339.762776] write_header = 0xf827e000. [ 339.762783] read_header = 0xf827e010. [ 339.762790] &write_header->w3 = 0xf827e00c [ 339.762796] &read_header->w3 = 0xf827e01c [ 339.762802] ape->table_virt = 0xee50a000. [ 339.762828] Allocated cache-coherent DMA buffer (virtual address = ef678000, bus address = 0x000000002f678000). [ 339.762859] writing 0x000400ff to 0xf827e010 [ 339.762868] writing 0x00000000 to 0xf827e014 [ 339.762876] writing 0x2e50a000 to 0xf827e018 [ 339.762883] Flush posted writes [ 339.762888] [ 339.762891] Start DMA read [ 339.762898] writing 0x000000fe to 0xf827e01c [ 339.762906] EPLAST = 64222 [ 339.762911] POLL FOR READ: [ 339.762918] EPLAST = 64222, n = 254 [ 339.763026] EPLAST = 64222, n = 254 [ 339.763136] EPLAST = 64222, n = 254 ... [ 339.773754] EPLAST = 64222, n = 254 [ 339.773870] [ 339.773874] Start DMA write [ 339.773881] POLL FOR WRITE: [ 339.773888] EPLAST = 64222, n = 254 [ 339.773997] EPLAST = 64222, n = 254 [ 339.774108] EPLAST = 64222, n = 254 ... [ 339.784752] EPLAST = 64222, n = 254 [ 339.784867] [ef678000] = 0xef678000 != [ef67a000] = 0xef67a000 ?! [ 339.784879] [ef678004] = 0xef678004 != [ef67a004] = 0xef67a004 ?! [ 339.784890] [ef678008] = 0xef678008 != [ef67a008] = 0xef67a008 ?! [ 339.784901] [ef67800c] = 0xef67800c != [ef67a00c] = 0xef67a00c ?! [ 339.784911] [ef678010] = 0xef678010 != [ef67a010] = 0xef67a010 ?! [ 339.784922] [ef678014] = 0xef678014 != [ef67a014] = 0xef67a014 ?! [ 339.784933] [ef678018] = 0xef678018 != [ef67a018] = 0xef67a018 ?! [ 339.784943] [ef67801c] = 0xef67801c != [ef67a01c] = 0xef67a01c ?! [ 339.784954] [ef678020] = 0xef678020 != [ef67a020] = 0xef67a020 ?! [ 339.784962] ---more errors follow! not printed--- [ 339.784970] DMA loop back test FAILED. [ 339.784983] bar_tests() end, result -1 [ 339.784990] probe() successful. I'm using a Atom processor which is running Ubuntu 10.04 32 bits, and a Altera Arria II GX with the PCI / Chaining DMA example synthesized on Quartus 11.1. I've been around this for some days now, so any suggestion would be greatly appreciated. Best regards, PedroHi pete_san,
I have a host PC running linux (Ubuntu 10.04 LTS 64) and connected to an DE4 Stratix IV over PCIe. I explore the use of the FPGA as co-processor, but i get same problem of yours. Yes, I follow this tutorial (http://www.google.com.br/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&ved=0cewqfjae&url=http%3a%2f%2fsoftware.intel.com%2ffile%2f42901&ei=blb7t4tnmyyugqeapiszaw&usg=afqjcnf90cjh8c7rcs5pauelhv2jip6cja) and it work fine at Windows. I saw in your design that you used 15 bit in BAR but only has mapped 8 bit, it's correct! Best Regards, HaulissonHi Haulisson.
After checking the document, I think the DMA core you're using is not the one the kernel module is designed to use. The 'altpciechdma.c' is oriented for the chaining DMA core, which I don't exactly know where it is described, but you can find references to it in the chapter 15 of 'IP Compile for PCI Express User Guide' Altera document. But I believe the document you showed me uses the standard DMA core. When instantiating the DMA core in the Qsys, click in the button 'Documentation' to get its datasheet. I believe you'll find that the registers configured by the kernel module do not match those of the datasheet. If that's the case, you might have to alter the module's 'dma_test' function yourself, to configure the DMA core registers. Best regards, PedroHi pete_san
I made probably the altpciechdma.c execute fine here. Thus, I'd like to test my drive in user level with simple write and read example , but i don't know how! I saw some things about ioctl, but no success. Do you has some suggestion? Best RegardsHi haulisson.
This short tutorial will give you all the information you need: http://tuxthink.blogspot.com/2010/10/writing-example-driver-from-scratch.html You'll find that most of the 'character device' code is already implemented in the altpciechdma.c driver. You can then complement it with the system calls 'copy_from_user()' and 'copy_to_user()', and use the provided user space code to achieve your goals. Best regards, PedroHi,
most of you might have already found a solution for your problems. I just would like to point out a few things regarding altpciechdma driver. I have managed to make it run on a Ubuntu 10.04 64 bits. Some of you have an error where the dma loopback test do not match the transfer (as if no buffer overwrite is performed). if your system has a 64 bit manageable DMA, the driver might recognise the PCI implementation as capable, but the hardware has to know it too. There is a generic parameter on the chain-dma design where compatibility for 64 RC DMA modules must be configured. On the other hand, I am now trying to use the driver to build the character/block device required to keep working. If anyone has some experience on this, it would be nice to have some suggestions on how I should proceed. Thanks to everyonethanks arco,
I found it in pcie_ddr2_a2gx. it is not so obvious in qsys (perhaps none). this will set the appropriate TLP in altpcierd_cdma_app_icm_ddr which eventually controls altpcierd_dma_dt, etc... i was thinking to do my hardware development with reference design with qsys since it is simpler, but i think pcie_ddr2_a2gx is more detailed in implementations also complex. or do you know how to set these things in Qsys? thanks once again.Sorry for my late reply,
the parameter I mention is located on the VHDL/Verilog design. I am not aware if it is possible to access it from Qsys. I hope it solved any doubt on your design. Anyway, good luck and patience.Thanks arco!
I would like to get anyone opinions on http://www.alterawiki.com/wiki/linux_pcie_driver and ftp://ftp.altera.com/up/pub/altera_material/12.1/tutorials/using_pcie_on_de4.pdf It seems easier due to Qsys.. Thanks alot in advance!Hi,
I can't find the file "mapper_user_to_sg.h" and "user_dma_sg.c". The web http://www.sidebranch.com/leon/user_dma_sg.c svn.assembla.com/svn/altpciechdma/user_dma_sg.c also can't be visit. There is any advise for me? Thanks.