How to generate clock in altera ep2c5t144c8 board?

Altera_Forum · ‎08-29-2015

Hi!

I am facing problem for generating clock in ep2c5t144c8 board of altera quartus II.

I have tried many times to set the clk in time quest analyses but it is not

giving any response when I check my desired signal on oscilloscope!

I have attached the screen shots of 'create clock' and 'name finder' windows.

everyones response will be highly appreciable!

Thank you!


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library STD;
use STD.TEXTIO.all; 
--use ieee.std_logic_arith.all;
entity pwncheck is 
port (
clk         : in std_logic;
reset     : in std_logic;
led       : out std_logic);
 
 
 end pwncheck;   
 architecture operation of pwncheck is 
 signal count_pwm_freq : unsigned(11 downto 0);
 signal set_pwm_duty   : unsigned(11 downto 0);
 signal freq_pwm_maint : unsigned (11 downto 0);
 begin 
 process(clk,reset)
 begin
 if (clk'event and clk = '1')then  
                    count_pwm_freq <= count_pwm_freq + 1;
                    --"010011100010" ;--010011100010=>1250
                        if (count_pwm_freq = 010011100010)then
                            led <='0';
                            else if (count_pwm_freq = "100111000100")then --100111000100=>2500
                                        count_pwm_freq <= (others => '0');
                                        led <='1';
                            end if;
                        end if;
                end if; --clock
end process;
end operation;

Altera_Forum · ‎09-01-2015

Change if (count_pwm_freq = 010011100010)then

to if (count_pwm_freq = "010011100010")then

Cheers,

Alex