How to get access to signals in SOPC blocks

[Altera_Forum]

Hi, 

 My problem is that I got an Altera SOPC IP block (clocked video out), which I need to be able to reset under NIOS software control. The IP block does not have a control bit that can clear/restart the IP core properly. So my idea is to connect the hardware signal "rst" of the IP block to an output pin controlled by the NIOS.    Since the signals for the Clocked video out IP are connected to the "fabric" in the SOPC, and thereby handled by the SOPC builder, I don't seen how I can get to the "rst" line. I have considered making a "wrapper" for the IP core (mounting the IP core inside the wrapper as a component (using VHDL)), but not sure how, since the Altera IP core are encryped. We have only license to use the VIP cores, not viewing source.   Any ideas?   Otherwise I'll probably need to write a complete clocked video out function instead :(    BR Peter

[Altera_Forum]

This is my one big complaint with Altera. They keep an extremely tight lock on their IP cores whereas other vendors will often provide reference designs. The problem with this is that many of the cores either have bugs or are lacking features and you are simply stuck. 

 I myself am experiencing a great deal of grief with the 8.0 version of the Video IP. Particularly with the clocked input, deitnerlacer, and mixer. And I can't really do anything about it other than rewrite the cores. The video IP is one area where the source code should be made available as there is no way a one size fits all approach will ever be true with video.  However, here is the solution to your problem ...  Create your clocked output core using the megawizard rather than placing it in SOPC builder. Then create a wrapper around the generated core and create your own custom SOPC component. This will give you access to the reset line however you choose to use it. You could even add an extra register address in the wrapper and control it that way.  Jake

[Altera_Forum]

Yes I agree, having access to the HDL would help a lot. Not only when it is necessary to modify, to get it working, but also because the documentation (of the VIP cores) is rather bad - having a peek in the HDL might help debugging. 

 I followed your suggestion, and added a wrapper around the core. Works fine now - Thanks!   /Peter