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I need to implement an histogram in a FPGA for 2D image frames.
Any suggestion or reference design??? Thanks in advance.Link Copied
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Take a RAM block full of zeros
As each pixel comes in, use it as an *address* into the RAM block, take the data, increment it and write it back in. If your FPGA clock is less than 2x the pixel clock, you need to be a bit cleverer to account for the RAM read latency... Cheers, Martin- Mark as New
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Hi Martin,
Thanks a lot for giving to me such a good trick, I've got implemented it in dspbuilder and i'm testing it using Simulink. At this point I've have the histogram values within a double port RAM, but i have some doubts about how get the statistical mode. I've attached a part of my design for more information. best regards!!!- Mark as New
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For the mode, don't you just find the histogram bin with the highest value in?
At the end of the frame, go through each address in the histogram with a counter and latch the address and data values if the data is bigger than your previous "biggest value". Cheers Martin- Mark as New
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Ok martin, I'll try using a latch, thanks again!!!
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Latch might not have been the best choice of terminology on my part - what I meant was a set of flipflops which are enabled only when you want to store data in them (ie when you have a new "biggest value"). I didn't mean a latch in the old 7475 latch sense - They're usually a bad idea in FPGA-land!
Cheers, Martin- Mark as New
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OK Martin I know what you wanted to mean, I'm trying to do using two 8 bit d-type flip-flop updating the new maximun value of the frequency and the value associated.
Your explanation was enough for me. Are you currently working with FPGA's??? or just in image processing? regards- Mark as New
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i've got a project to write a VHDL program for Histogram computation of a 16x16 grey image...... can you please guide me on how to do it?? i'm new to vhdl and fpga's......
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--- Quote Start --- i've got a project to write a VHDL program for Histogram computation of a 16x16 grey image...... can you please guide me on how to do it?? i'm new to vhdl and fpga's...... --- Quote End --- This thread already gives you a few good hints.

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