I'm trying to do a very similar thing, but am using a IS61WV102416 (1024k x 16bit) part. If I understand things correctly, I need to specify an address width of 20 in the example TCL file. This causes SOPC builder to generate an address interface that is defined as an vector of 21 logic lines. For example:
signal address_to_the_async_sram : out std_logic_vector (20 downto 0);
The line connections from the FPGA to the SRAM would then dictate that I connect address_to_the_async_sram(20) to A19, address_to_the_async_sram(19) to A18, ..., address_to_the_async_sram(1) to A0. In other words, the LSB of address_to_the_async_sram would need to be ignored.
I'd also need to have the byteenables connected to be able to properly write to the device. Without these, byte write access is impossible (not driving the 'unused' side of the data lines to a high impedance.)
Does this sound correct?
