How to manually place PLL

[Altera_Forum]

I've been looking through the forums and have only found one post about this. It didn't help me because I got an error when trying to follow it. My issue is that I have to modules each having their own PLL block from the mega wizard (altpll). When I synthesize the project with them one PLL is place over the other one it looks like. If I do one at a time and output the clocks to a pin each module outputs the expected clocks. When I add them together they don't. When I look at the chip planner I can only see one of the PLLs instantiated in a PLL block and not the other. So the chip planner looks like it has 3 empty PLLs and 1 being used when it should be 2 and 2 (empty/used).  

 So I am trying to use the assignment editor to specify where to put one of them and am getting these errors during fitting. It is a bit hard to follow so the key errors are broken out with *************.    Info (15099): Implementing clock multiplication of 1, clock division of 250, and phase shift of 0 degrees (0 ps) for I2CMasterController:i2c_tx_master_0|I2C_TX_Master_PLL:I2C_TX_Master_PLL_inst|altpll:altpll_component|I2C_TX_Master_PLL_altpll:auto_generated|wire_pll1_clk[0] port Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. ************** Error (171011): Can't assign node "I2CMasterController:i2c_tx_master_0|I2C_TX_Master_PLL:I2C_TX_Master_PLL_inst|altpll:altpll_component|I2C_TX_Master_PLL_altpll:auto_generated|pll_lock_sync" to location PLL_3 -- node is type Register cell ************* Error (171011): Can't assign node "I2CMasterController:i2c_tx_master_0|I2C_TX_Master_PLL:I2C_TX_Master_PLL_inst|altpll:altpll_component|I2C_TX_Master_PLL_altpll:auto_generated|locked" to location PLL_3 -- node is type Combinational cell *************** Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Error (171000): Can't fit design in device Error: Quartus II 64-Bit Fitter was unsuccessful. 3 errors, 1 warning  Error: Peak virtual memory: 679 megabytes  Error: Processing ended: Fri Aug 08 18:53:41 2014  Error: Elapsed time: 00:00:06  Error: Total CPU time (on all processors): 00:00:07 Error (293001): Quartus II Full Compilation was unsuccessful. 5 errors, 3 warnings  Here are some screens of the assignments window  https://www.alteraforum.com/forum/attachment.php?attachmentid=9233   https://www.alteraforum.com/forum/attachment.php?attachmentid=9234   I tried following this post:  http://www.alteraforum.com/forum/showthread.php?t=4255  I don't understand how I'm getting a fitting error here when selecting the PLL since this is all auto generated by the megawizard. What am I missing here?  Thanks, Rob

[Altera_Forum]

Ok so I figured out why Quartus couldn't find my PLL's. I had to add a |pll1 when I used the assignment editor to select the path to each PLL. So my paths are as follows for an example: 

 I2CMasterController:i2c_tx_master_0|I2C_TX_Master_PLL:I2C_TX_Master_PLL_inst|altpll:altpll_component|I2C_TX_Master_PLL_altpll:auto_generated|pll1 I2C_Controller:sm5882_0|SampleClkPll:SampleClkPLL_inst|altpll:altpll_component|SampleClkPll_altpll:auto_generated|pll1  I have run into another problem after this though. Now, Quartus says the location assignments of the PLL's are not compatible -hence the PLLs can't be merged. I'm not trying to merge them. I have two PLLs I want to be seperate. Why is Quartus trying to merge these two PLLs? I only have a single 50Mhz clock in on this development board driving the input of both PLLs...is this why Quartus is trying to merge them? It seems unreasonable that you would have to have two different input clocks to achieve two seperate PLLs.  Attached is my message log from the message window. The exact warnings above are in there but in full text.