How to measure the data throughput of TCP/IP connection between a FPGA and PC?

Altera_Forum · ‎02-17-2011

Dear all,

Currently I'm developing an Gigabit Ethernet interface between a DSP board and a PC on Stratix IV FPGA. The DSP board sends continuous data to the FPGA, then the FPGA forwards them to PC via TCP/IP connection.

My question is how to measure the TCP/IP data throughput from the FPGA to PC? :confused:

Thanks

Altera_Forum · ‎02-17-2011

Why not a simple division between the amount of data transmitted and the time required?

This is straightforward since you say your data flow is continuous. It can be done either on fpga or on pc side.

Altera_Forum · ‎02-17-2011

can't you count data size?

when you begin transfer.

save current time on memory of PC.

and save the time when it's finished.

so you have those information.

- start time

- end time

- and data-size

the answer is data-size/(end time - start time)

or, if you can't get start time on your PC.

get testpin from the Stratix.

you can see the term of transfer with your oscilloscope somehow.

is that good for your answer?

Altera_Forum · ‎02-17-2011

Hi, thanks for your reply :)

Yeah, I'm also thinking like what you suggest to me. For hand calculation of course we can calculate the throughput using those ideas. But I'm still wondering whether this calculation result really represents the actual throughput or not.

@akira

what kind of testpin do you mean? would you give me any URL / document about this testpin?

Thank you.

Altera_Forum · ‎02-17-2011

The calculation is accurate as much as your timer is. Generally, longer the run time (so the amount of data transmitted), better is the result, because you take a longer average on the transfer rate.

With test pin akira meant you can set a fpga output when you start sending data and reset it after you have sent a known data payload, say 100MB. Then you can measure the pulse on that pin with an oscilloscope and get the data-send rate. If the pulse length is 4sec, then you easily get rate=100MB/4s = 25MB/s

This way you don't need a timer in fpga.

Cris

Altera_Forum · ‎02-17-2011

actually Cris72 answered what I wanted to say.

but you want to know what test pin meant in this case.

I will describe it as much as I can.

see attached file "figure1.jpg"

this is simple block diagram of your system right?

also see "figure2.jpg"

inside of StratixIV, it has an IP-core( or cores) to communicate to DSP board.

it may have some other pins which are not connected currently or not important to use.

see "figure3.jpg"

if you know what IP cores do.

you can get start signal and end signal.

put the signals on the PIO-pins.

then you can see when transfer starts and ends.

if you don't know what I am saying, you'd better forget what I say.

studying this skill takes some days.( or even months)

guessing why you think your calculation maybe wrong is.

the result is too slow compare to 100MB/sec. isn't it right?

TCP/IP is not as fast as its theory.

if you got 10MB/sec.this is the result of it. At least for now.

bye bye:D