How to put 2 or more fifos into 1 M9K in C3 device

[Altera_Forum]

How to put 2 or more fifos into 1 M9K in C3 device 

 hello,everyone:  In a module(I use CYCLONE III device),I use 4 fifos from megafuntion.The 4 fifos are all very small,but ervery need 1 M9k(or 2,because the width is 64 ),that wastes a lot of M9k resouse.    Does it have a method to put multiple fifos into 1 M9K.  Thank you for your help.

[Altera_Forum]

Synchronous or asynchronous? 

A FIFO requires two independent address ports, so two FIFOs requires four addresses. The M9K only has two. So there is no easy way. You could timeshare a memory block, running it at 2x the speed and therefore doing twice as many reads/writes per clock. You would have to use your own FIFO or hack the megafunction(which is probably AHDL) and hence not very easy. You could build one of the FIFOs out of logic elements, but that's quickly inefficient and I'm assuming you thought of that and ruled it out.

[Altera_Forum]

--- Quote Start ---   You could timeshare a memory block, running it at 2x the speed and therefore doing twice as many reads/writes per clock.   --- Quote End ---    Hi Rysc,  I don't see time sharing applying here because you need the fifo pipe to stay for one signal and so you can share read/write but not the pipe which obviously defeats the purpose unless you use double data width to make the share but then you will need same push on pipe. So overall I don't see this suggestion useful unless you have some thing else in mind.

[Altera_Forum]

The FIFOs can be merged if they have same control pins and data lines. Otherwise You have no choices.

[Altera_Forum]

Kaz, 

I think it would still work, even with the pipe(although the output register could be removed). It's like time-sharing a DSP block, which could have multiple pipes in its path, it would just be running twice as fast and hence reading/writing data for each FIFO over the course of one regular clock cycle. The control/feedback paths are outside the memory, and would not be time-shared. It's still not trivial, but I think it would work.

[Altera_Forum]

May be you mean if ram block depth is enough for say two fifos then yes you can run at double speed but you need to design the addressing and other control signals to take turns. I was referring to ready made fifos by altera in which case you can't control the addressing and therefore can't share the pipe.

[Altera_Forum]

Yeah, you'd have to use a custom RTL FIFO. I think the megafunction can be dived into, but it would not be easy.

[Altera_Forum]

Timesharing is how the multi-channel FIFO in SOPCB/Qsys is implemented as well (and as far as I'm concerned the only way multiple FIFOs can be implemented using a single RAM block). That IP doesn't rely on SC/DCFIFO so you could take a look at the source code for it... or use it directly since it was developed for what you are trying to do. 

 I'm pretty sure it doesn't do any sort of double, triple, quatruple, etc... rate matching, it just back pressures the other ports when something else is accessing the same port of the FIFO.

[Altera_Forum]

thanks ,everyone!! 

 one more qusetion! I found that when I set the data width(same depth, for example 4),if I set it more than 36,it need one more M9K,even though the depth is very small. Why like this,please?   ps,the fifo I used is synchronous FIFO

[Altera_Forum]

How much is VERY small? M9K is 9kb size, if interface is 36bits, then the depth can't be more than 256.

[Altera_Forum]

The max width is 36 bits. The device handbook has all the details of what you can and can't do. Note that the muxing and routing into/out of the memory blocks is pretty expensive in silicon. It's easy to just think about number of bits, but number of ports and there size is a significant portion of how many you can put into a device. Altera has done stuff like 3 different memory sizes, including huge memories(512K on older devices), to try and accomodate different user requirements.