How to receive LVDS ADC data

[Altera_Forum]

Hi, 

My design is still using cyclon I, EP1C4F324C6. It will connect to a serial output A/D conveter which has four lines (represent four channel outputs) and one frame line and one clock line. All lines are LVDS ones. The channel bit rate is 280Mb/s and the frame (it has 14 bits) cycle is 50ns but clock frequency is 140MHz. Both its rising edge and falling edge indicate the data content. How to design the FPGA to receive the serial data? Should i use LVDS transceiver IP? But,I do not have any extra PLL. Or, is there any other way? I tried to use gate logic to receive it directly but it failed at the frame cycle less than 140ns(upto 7Mhz). The problem is i need a globle clock over 560MHz. It looks like impossible for Cyclon I. I am a beginer. Any helps and suggestions are very appreciated!

[Altera_Forum]

Use an altddio_in MegaFucntion and clock it by the ADC bit clock, preferably through a dedicated clock input. 

 I don't understand why you should need a 560 MHz clock for 280 MHz bit rate.

[Altera_Forum]

Thanks. I am gonna try. Will report.

[Altera_Forum]

Hi, 

It looks like it is working. For EP1C4F324C6 I use a quadrant as a LVDS I/O port area. I cound not find which are specific clock inputs. I need four of this kinds of clock inputs. Currently it works under speed of 280Mb/s of LVDS input bit stream with the data clock of 140Mhz. When the speed reaches to this extrem value the data is unstable. Data error ocurrs.  Any sugestions will be very appreciated!

[Altera_Forum]

The method should work with considerably higher speed. Timing constraints reflecting the ADC signal timing may be necessary.

[Altera_Forum]

The two clocks going to two altddio with the same clock settings turns out a warning after the full compilation. It says that one of the clock settings has been igored. Why? Thanks for your help!