How to select I/O standard in pin planner

[Altera_Forum]

Hi, everyone 

 I'm trying to understand a sample program in Arria II Gx development Kit.  By assigning proper signals and clock to a connected SDI daughter board, the daughter board can feedback 147.5MHz to FPGA.   When I use 2.5V(default) as the I/O standard for the clock pin of 147.5MHz, my Verilog program cannot detect the rising edge and a simple counter cannot work. However, when I change the I/O standard to LVDS, the counter works.  After solving this problem, I check the pin planner of the sample program and find out that there are lots of I/O standards assigned to the pins of different components. For example: SSTL18-class I for DDR2 and 1.5V PCML for transceiver...  Is there any document related to the selection of I/O standard in pin planner?  Thanks.

[Altera_Forum]

--- Quote Start ---   Is there any document related to the selection of I/O standard in pin planner?   --- Quote End ---  Yes, its called the schematic for your board.  FPGA I/O pins can be connected in a huge number of ways. The board designer will determine how many logic standards are needed, connect the power supplies appropriately, and then hopefully document the I/O standards required for the board.  If you do not have a 'user manual' that describes the I/O assignments, then the schematic is the document you need to review. You can generally figure out the I/O standard required based on the VCCIO used on a particular bank, and from the data sheets of the devices that the FPGA is connected to.  Cheers, Dave