tesleft,
The complexity required depends on exactly what you are trying to do. Are you trying to communicate with the FPGA from a host with a dedicated link? Or does it need to go across a network? Do you need unidirectional or bidirectional traffic? If you have a direct connection, you can simplify things. I use a direct connection (fpga <-> external processor) often, and I keep everything at layer 2 (mac dst, mac src, length, payload, crc) in order to reduce unnecessary overhead, so I don't need an IP stack. Depending on where your comforts like (as far as HDL vs C), you could do a lot of the work in a nios, which can write the entire packet to a ram, and then signal the fabric to transmit the contents of the ram. If you don't know the host mac address, you can either setup the host in promiscuous mode, or the host will have to send data and you'll have to capture its mac address. If the host needs to send the fpga data, and you can control the host, you can enter a static arp entry in the host so you don't have to support arp reply.
Keep in mind if you're sending a small amount of data in a packet, you'll likely have to pad it so the packet reaches 64B in size (min packet size). As Daixiwen said, it's not super simple, but depending on the application you can make life a little easier.
Cheers.
