How to set internal pul-up/pull-down to an FPGA pin in Quartus ?

Altera_Forum · ‎05-25-2015

Hi Can somebody let me know how to make a FPGA pin to be connected with an internal pull-up or pull-down resistor ?

Also I would like to know how to verify from the reports generated from the Quartus run - for which are all the pins has been connected to the internal pull-up or pull-down ?

Thanks and Regards,

Prasanna

Altera_Forum · ‎05-25-2015

You may do so in either the assignment editor or the pin planner or the QSF file.

then you can check back in the fitter report to see if the assignment

Altera_Forum · ‎05-25-2015

If you are referring to reserving unused IO pin to pull up/down internal, you could do the following:

1. Open up QII pin planner

2. Right click on a IO pin

3. Look for Reserve

4. Then select if you want the reserved pin to be connected to VCC or GND.

You can then verify the compilation through .pin file or Fitter report.

Altera_Forum · ‎05-25-2015

For unused I/O pin setting, you can also reserve the unused I/O pin as input tri-stated with weak pull up from the Device and Pin Options.