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Beginner
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How to set up Cyclon 10gx transceiver 10g base SR (Short Range 850nm MMF)/LR(Long Range 1310nmSMF )/ER?

 

 

Hello,

  • I'm using the device of cyclon10gx, and I use the high-speed transceiver in it. My preset protocol is 10g base r..However, one of my clients USES an xilinx FPGA,We'll have optical communication
  • , and his 10G BASE R protocol needs to set up a 10G BASE SR or 10G BASE LR.
  •  
  • So,I want to know :
  •  
  • 1 ,can I set this in the high-speed transceiver of c10gx,How do I set up the correct docking?

 

 

2, Use the high-speed transceiver of c10gx to preset 10g base r. Should the single-mode(SM 850nm) optical module(SFP+) or multi-mode optical module be used?

 

THANK YOU! 

 

This is my setup for the high speed transceiver using the C10 device

 

ECUW(AYU0BKKBGL](M8659P.png

 

 

 

 

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3 Replies
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Moderator
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HI,

 

Pls see my reply below.

 

  1. 10G BASE SR or 10G BASE LR setting in NativePHY
  • At the top of NativePHY IP gui, there is one section called "transceiver link type" where user can select either SR or LR option.
  1. Use the high-speed transceiver of c10gx to preset 10g base r. Should the single-mode(SM 850nm) optical module(SFP+) or multi-mode optical module be used?

 

Thanks.

 

Regards,

dlim

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Beginner
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  • 1 Thank you very much, I've noticed the options in the NATIVEPHY IP GUI called  "transceiver link type",But here's the explanation is RS :Chip to chip coummunication ;I don't know if this is the same as the" sr" in the 10gbase r protocol,
  • Now I know. Thank you very much
  • 2 My transceiver link type was selected as SR. I found in the actual test that both multi mode fiber and single mode fiber could receive data, but there was always a bit error rate, which may be caused by the incompatibility of the optical module I chose
  • 3 The XGMII interface data I receive sometimes has a bit of an order reversal, for example : The correct data should be :07060504_03020100; But sometimes the data I received was 03020100_07060504, and It's correct most of the time
  • Have you ever encountered a similar situation in this respect? Is it the same as the second problem? Is it caused by the incompatibility of the multi mode fiber I chose?
  •  
  • Thank you very much for your patience!
  •  

 

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Highlighted
Moderator
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HI,

 

The SR and LR in NativePHY IP basically means short range (chip to chip) setting and long range (chip to backplane) setting irrespective of protocol.

  • FPGA to SFP is consider as "chip to chip" connection
  • So, you should set it to SR for your case

 

Regarding BER error debug

  • Perhaps you can try enable PHY loopback to isolate is this board related issue or FPGA internal issue first

 

For the data swap issue and not data corruption issue

 

Thanks.

 

Regards,

dlim

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