How to share one PLL and DLL by two DDR3 interfaces

[Altera_Forum]

Hi Folks, 

 I have a Cyclone V GX FPGA Development Board. There are six DDR3 components on the board, three are on the bottom side of 5CGXFC7D6F31C7NES and the others are on the right side. Now I'm gonna use a bottom ddr3 component and a right ddr3 component and I want the two DDR3 interfaces can share one PLL and one DLL.  My Quartus II Version is 13.1 and Both the DDR3 interfaces operate at 300MHz in the half-rate mode.  It is possible accroding to emi.pdf  https://www.alteraforum.com/forum/attachment.php?attachmentid=8937   My design meets the above criteria. But when Quartus II compils My design, there are sereval errors reported by Fitter.   Error (175001): Could not place dual-regional clock driver Info (175028): The dual-regional clock driver name: ddr3_inf1:ddr3_master|ddr3_inf1_0002:ddr3_inf1_inst|ddr3_inf1_pll0:pll0|pll_addr_cmd_clk~CLKENA0 Error (177002): The Fitter could not use locations for destination pin that were in the same clock region as the dual-regional clock driver Info (175027): Destination: pin mem1_cke[0] Info (175015): The I/O pad is constrained to the location PIN_L28 due to: User Location Constraints (PIN_L28) Info (175029): 136 locations affected Info (175029): CLKCTRL_R64 and CLKCTRL_R82 Info (175029): CLKCTRL_R64 and CLKCTRL_R83 Info (175029): CLKCTRL_R64 and CLKCTRL_R84 Info (175029): CLKCTRL_R64 and CLKCTRL_R85 Info (175029): CLKCTRL_R64 and CLKCTRL_R86 Info (175029): CLKCTRL_R64 and CLKCTRL_R87 Info (175029): CLKCTRL_R65 and CLKCTRL_R82 Info (175029): CLKCTRL_R65 and CLKCTRL_R83 Info (175029): CLKCTRL_R65 and CLKCTRL_R84 Info (175029): CLKCTRL_R65 and CLKCTRL_R85 Info (175029): CLKCTRL_R65 and CLKCTRL_R86 Info (175029): CLKCTRL_R65 and CLKCTRL_R87 Info (175029): and 124 more locations not displayed   Error (177002): The Fitter could not use locations for destination pin that were in the same clock region as the dual-regional clock driver Info (175027): Destination: pin mem1_a[7] Info (175015): The I/O pad is constrained to the location PIN_AC30 due to: User Location Constraints (PIN_AC30) Info (175029): 100 locations affected Info (175029): CLKCTRL_R0 and CLKCTRL_R10 Info (175029): CLKCTRL_R0 and CLKCTRL_R11 Info (175029): CLKCTRL_R0 and CLKCTRL_R12 Info (175029): CLKCTRL_R0 and CLKCTRL_R13 Info (175029): CLKCTRL_R0 and CLKCTRL_R14 Info (175029): CLKCTRL_R0 and CLKCTRL_R15 Info (175029): CLKCTRL_R0 and CLKCTRL_R16 Info (175029): CLKCTRL_R0 and CLKCTRL_R17 Info (175029): CLKCTRL_R0 and CLKCTRL_R18 Info (175029): CLKCTRL_R0 and CLKCTRL_R19 Info (175029): CLKCTRL_R1 and CLKCTRL_R10 Info (175029): CLKCTRL_R1 and CLKCTRL_R11 Info (175029): and 88 more locations not displayed   Error (177002): The Fitter could not use locations for destination pin that were in the same clock region as the dual-regional clock driver Info (175027): Destination: pin mem2_a[10] Info (175015): The I/O pad is constrained to the location PIN_AJ8 due to: User Location Constraints (PIN_AJ8) Info (175029): 36 locations affected Info (175029): CLKCTRL_R70 and CLKCTRL_R76 Info (175029): CLKCTRL_R70 and CLKCTRL_R77 Info (175029): CLKCTRL_R70 and CLKCTRL_R78 Info (175029): CLKCTRL_R70 and CLKCTRL_R79 Info (175029): CLKCTRL_R70 and CLKCTRL_R70 Info (175029): CLKCTRL_R70 and CLKCTRL_R71 Info (175029): CLKCTRL_R71 and CLKCTRL_R76 Info (175029): CLKCTRL_R71 and CLKCTRL_R77 Info (175029): CLKCTRL_R71 and CLKCTRL_R78 Info (175029): CLKCTRL_R71 and CLKCTRL_R79 Info (175029): CLKCTRL_R71 and CLKCTRL_R70 Info (175029): CLKCTRL_R71 and CLKCTRL_R71 Info (175029): and 24 more locations not displayed  Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.     I can not find the correspoding solutions in the emi.pdf and Cyclone V handbook, so I upload the project file for help. Any help would be appreciated.      Best Regards, -spectrum

[Altera_Forum]

Hi, 

 First, I have to admit that I haven't been checking your QAR out. I just wanted to check if you have tried to assign the clock signal to a global net rather than a dual-regional one. Maybe you have selected to use an interface on the bottom left together with an interface on the top right?   Regards J