How to synchronize a PLL with a clock signal

Altera_Forum · ‎01-04-2013

In my design I require there to be a 100 mhz clock signal and a 50 mhz clock signal. I have an 50 mhz clock source so I decided to use a PLL to convert it to a 100 mhz clock. The only issue I have is that the 2 clocks have to be synchronized as it is in this image.

https://www.alteraforum.com/forum/attachment.php?attachmentid=6630

It has to be precise or else they may be an issue. Is there any way to do this?

Altera_Forum · ‎01-04-2013

Use the appropriate PLL compensation mode.

Altera_Forum · ‎01-04-2013

How would that be done? I am using a megafunction and the closest thing I can find is Source-Synchronous compensation mode. Is that the mode that I need to enable?

Altera_Forum · ‎01-04-2013

You don't say whether this clock alignment is needed internal to the FPGA or external to the FPGA.

If it is internal, then just use the 50MHz as the PLL reference, and have the PLL generate *two* output clocks; 100MHz and 50MHz. Those two outputs will be synchronous. The phase of these two signals relative to the input 50MHz will change depending on the PLL mode, but that only matters if you have external logic clocked by the 50MHz reference that you then need to send data from registers clocked by the PLL output signals.

Cheers,

Dave

Altera_Forum · ‎01-04-2013

A PLL always produces a feedback clock that's phase aligned to the input clock (hence the name, phase locked loop).

The several compensation modes in the megafunction let you choose the feedback path. You need to read a bit about each one and see which fits your needs.

http://www.altera.com/support/devices/pll_clock/glossary/pll-glossary.html#c

Altera_Forum · ‎01-04-2013

Bring the 50 MHz clock into the PLL, and then create two output clocks; one at 50 MHz and the other at 100 MHz. Don't use the input 50 MHz for anything except to feed the PLL. Use the 50 MHz output from the PLL inside your design. The 50 and 100 MHz clocks from the PLL will then be phase aligned to their rising edges by design, guaranteed every time out of reset. It will always look like your top timing diagram, not the bottom one. This is independent of feedback mode.