Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20867 Discussions

How to synchronize the inputs of multiple ADC chips using the JESD204B IP core in an FPGA?

allen18
New Contributor I
823 Views

        Hello everyone, I have encountered some issues in designing an FPGA solution for receiving ADC data. The FPGA I am using is stratix10-1SX110HN2F43I2VG, which has two tiles, with each tile having 4 banks. Each bank has 6 channels and two reference clock inputs.
I need to use the JESD204B interface to synchronize the inputs of 8 ADC chips. I have checked the IP core guideline, which tells me that I need to instantiate 8 IP cores for the 8 links. I plan to use 4 lanes for each IP core, requiring a total of 32 channels.
        I intend to use the first H tile for 24 channels, accommodating 6 IP cores, while the remaining 2 IP cores will be placed in the second H tile. I also plan to distribute the device clock output from the LMK0482X chip to the reference clock of the first H tile, and I will also connect this clock to the PLL core to generate the frame clock and link clock.
       I plan to share the sysref signal connected to the FPGA to the 8 IP cores. Assign it to common IO pins ,because it's a low-speed signal .

      1.I want to know if the 8 IP cores in the two tiles can share the reference clock connected to the first H tile ?  If not, I may need to connect another device clock to the reference clock of the second H tile. These two clocks will be used for the 6 IP cores in the first tile and the 2 IP cores in the second tile.
      2.Another issue is that the LMK0482X chip can only output a maximum of 7 sets of device clocks and sysref signals, but my design seems to require 9 sets of device clocks and sysref signals or more. How should I design it more reasonably?屏幕截图 2023-08-18 192614.png屏幕截图 2023-08-18 192159.png屏幕截图 2023-08-18 193218.png

Labels (1)
0 Kudos
1 Solution
allen18
New Contributor I
670 Views

I have solved this problem. I used a clock buffer chip to replicate multiple sets of clocks.

View solution in original post

0 Kudos
3 Replies
ZH_Intel
Employee
747 Views

Hi Allen,

 

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

 

Thank you for your patience.

 

Best Regards,

ZulsyafiqH_Intel


0 Kudos
allen18
New Contributor I
671 Views

I have solved this problem. I used a clock buffer chip to replicate multiple sets of clocks.

0 Kudos
ZH_Intel
Employee
656 Views

Hi Allen,

 

Apologize for the delayed response as we encounter some technical difficulty.

Glad that your problem is solved, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Thank you.

Best Regards,

ZulsyafiqH_Intel


0 Kudos
Reply