How to use Avalon-MM Master BFM with Avalon-ST API Wrapper in VHDL test bench

[Altera_Forum]

Hi All 

  I will need to use a Avalon-MM-Master-BFM for a VHDL test bench. The DUT will be in VHDL. As the bfm are written in System Verilog, there is a wrapper call Avalon-MM-maser BFM with Avalon-ST API wrapper that is intend for the usage of VHDL test bench.   I have read through the Avalon bfm user guide, the description is kind of skim and there is no example showing how to use it.   Did you guys have any experience in using the wrapper in VHDL test bench? If you can share the experience, I would like to have an example in showing correct usage of it.  Thanks

[Altera_Forum]

--- Quote Start ---   Did you guys have any experience in using the wrapper in VHDL test bench? If you can share the experience, I would like to have an example in showing correct usage of it.   --- Quote End ---    The VHDL wrapper is pretty much useless. Its missing all the VHDL procedures needed to implement the API.  If you have a mixed language simulator (Modelsim full-edition), then you can just use SystemVerilog to test your VHDL device.  The other issue with using the Verification IP suite is that the checking logic uses System Verilog Assertions, so the bus monitors only work with a full version of Modelsim too.  Cheers, Dave

[Altera_Forum]

This is a link about document very useful for u: 

 http://www.google.com.vn/url?sa=t&rct=j&q=alvalon+interface+specification&source=web&cd=2&ved=0cc8qfjab&url=http%3a%2f%2fwww.altera.com%2fliterature%2fmanual%2fmnl_avalon_spec_1_3.pdf&ei=l0gvt92ndagqiqebx93wdg&usg=afqjcnewpwdeug5dt900cpkuzzsitwum-w&sig2=wwtg5blqyzvk7lqtnzgzow

[Altera_Forum]

Hello, please has anybody an example of test program for Avalon MM BFM generated in QSYS 13.1 in VHDL? How to access BFM API, I didn´t find any example or documentation.  

Thank you very much.

[Altera_Forum]

I noticed that the latest release of the Verification IP Suite supports VHDL, however, have not looked into it. This thread has a master/slave example using SystemVerilog 

 http://www.alteraforum.com/forum/showthread.php?t=32952&page=3  If you have Modelsim full-edition, you can use it directly to test your VHDL. If you only have Modelsim-ASE, perhaps it'll give you enough to get started ...  Cheers, Dave