How to use FPGA delay one signal edge in 1 ns while keep other edge unchange?

[Altera_Forum]

Hi, 

 Recently I am thinking is it possible to use a FPGA device do such kind of thing:  Use FPGA generate USART mater transmit signals, a 30Mhz clock, each clock cycle generate a bit data.  For the data, I want a little shift for each time transmit. How can I shift 1 ns for only one edge while all of the left edge keep some as before?  I am thinking if the internal logic run @ 800Mhz, for the special edge(The edge I want to shift), delay one clock cycle (1.25ns shift). But I don't know the PADs delay and board delay will affect the real delay I want? This way may not work. Any suggestion?

[Altera_Forum]

800mhz clock is far to fast for an FPGA.  

But what you want to do is more an IO pin delay spec. You cannot garantee specific delays inside an FPGA.  You need to use the set_output_delay sdc constraint in your .sdc file.

[Altera_Forum]

Hi Tricky, 

 Use internal 800Mhz clock to delay 1 clock cycle for the data, it's possible?

[Altera_Forum]

I want to change a little bit each time when I transmit data out, so constraint in sdc doesn't work for this.

[Altera_Forum]

400Mhz is about the fastest clock speed you can have in the top end FPGAs, and it requires a careful level of design. 800Mhz is no way achievable.  

Why do you want to do "little" changes?

[Altera_Forum]

This is sometimes done by making the wire for the clock slightly longer than the wire for the data. This could also be applied to traces on a PCB. Using the constraint Tricky mentioned above works by adding cells for the purpose of delaying the signal.

[Altera_Forum]

As I look at the SV device datasheet, the fastest clock tree speed is ~700MHz only which is lower than the 800 MHz. Note that this is the max specs and generally it would be difficult to achieve it. Considering timing closure issue, I think normally the core speed achievable would be much lower as Tricky mentioned.