Hello,
At the begining sorry for my lack of knowledge :-)
I'm using Stratix IV FPGA board with Altera Data Conversion Card. I want to receive data from ADC. When the usage of logic reaches 50% or more, then flipping of some bits occurs. I'm clocking this data with Data Clock output from ADC. My friend told me that the data must me latched in IOB cells - that's Xilinx name. I think in Altera it is IO Element. Can someone explain to me how to do it in quartus, using schematic view?
