How to use PLL in Cyclone II FPGA

[Altera_Forum]

Hi all, 

 I want to use PLL in my design.  I used quartus II(v7.2) megafunction to genarate a PLL. simulation results were proper. but when i m downloading the design to Cyclone II(EP2C8Q208C8) fpga i m not getting the pll output. Are there any setting to be done on FPGA to use PLL( like pll enable pin in stratix) PLL is in no compensation mode. and the pll is designed for 12Mhz. only one output (c0) is taken out with multiplication factor of 255/223.   Please Help...   Asha

[Altera_Forum]

Do you have a reset signal on the PLL? Check but I think it might be active-high.

[Altera_Forum]

Hi, 

thanks for the reply  ya i do have the reset signal and i checked it is not high. Actually I am able to see the simulation results but when i download the same design into device i am not able to see the output. Is there any signal that indicates the device that the PLL is being used? Can i assign the PLL outputs c0,c1,c2 to any of the I/O pins.   Please reply

[Altera_Forum]

But did you check whether the reset input on the PLL component is an active high or active low reset? 

 You can get the mega wizard to produce you a "locked" output on the PLL and/or connect the clock to an output pin.

[Altera_Forum]

The reset is active high and i have verified in simulation also. PLL locked output is also taken to a pin. In simulation the PLL lock output was seen but after downloading to FPGA the locked output is not coming.  

 please help

[Altera_Forum]

I think it should work OK down to 10 MHz. Have you tried a slightly faster clock just to see if that makes a difference? Are you certain that the clock is 12 MHz? Does the signal look OK on the board - i.e. no excessive overshoot, looks like a square rather than a sine wave etc?