How to use Shared pll in LVDS transmiter and resceiver functions

[Altera_Forum]

Hi, 

I am trying to use the shared pll function for LVDS transmiter and resceiver. AN479 says transmiter and resceiver must use the same input clock frequency. does it mean the tx_inclock of transmiter and rx_inclock of resceiver? cannot believe.:confused:

[Altera_Forum]

--- Quote Start ---  does it mean the tx_inclock of transmiter and rx_inclock of resceiver? cannot believe.  --- Quote End ---   What's your particular problem in understanding this simple statement? xx_inclock is the the respective PLL input clock (also called reference clock). If receiver and transmitter are sharing a single PLL, there can be only one reference clock.  It actually depends on your clock distribution scheme, if you can use a shared PLL. In some designs, it's possible.

[Altera_Forum]

In my design,  

for LVDS Transmiter, the tx_inclock is 40MHz, deserialization factor is 20, so tx_outclock is 800M . for LVDS Receiver, it will receive signal from the LVDS Transmiter.thus,rx_inclock should be 800M, deserialization factor is 20, rx_outclock is 40MHz. So, the tx_inclock and rx_inclock are different in my design, how can i use the shared PLL function to reduce the resource usage. Thanks!

[Altera_Forum]

According to the LVDS MegaFuction User Guide, rx_inclock is the receiver reference input clock. It can be exepected as an integer fraction of the bit rate, but very unlikely 800 MHz. 

 The more interesting question is, how you want to synchronize the receiver with the peer transmitter and where the latter is clocked from. It's also not said, if you'are using a FPGA family that has dynamical phase align features or if you have to achieve phase alignment manually.

[Altera_Forum]

--- Quote Start ---  In my design,  for LVDS Transmiter, the tx_inclock is 40MHz, deserialization factor is 20, so tx_outclock is 800M . for LVDS Receiver, it will receive signal from the LVDS Transmiter.thus,rx_inclock should be 800M, deserialization factor is 20, rx_outclock is 40MHz. So, the tx_inclock and rx_inclock are different in my design, how can i use the shared PLL function to reduce the resource usage. Thanks!  --- Quote End ---     I don't understand your reasoning. The serdes naturally implies a difference between "serial bit clock" (800MHz) and parallel clk(40MHz) since each 20 bits are processed in parallel. Can you explain further please...   The ref clk need not be equal to bit clk or the parallel clk

[Altera_Forum]

The Transmiter settings: 

1.number of channes:3 2.deserialization factor:20 3.output data rate:800Mbps 4.clock frequency:100MHz 5.use shared pll(s) for Rx and Tx The Receiver settings: 1.number of channels:1 2.deserialization factor:20 3.input data rate:800Mbps 4.clock frequency:100MHz 5.use shared pll(s) for Rx and Tx   I connected the rx_inclock and tx_inclock to a single clock source, but there needs 2 plls, seems that no merge action done.

[Altera_Forum]

It seems you misunderstood the serdes functionality. Why do you connect the two clocks you mentioned? 

 I assume your 100MHz is the ref clock for serdes PLL(it has nothing to do with data). The PLL should then produce two clocks: At Rx: the PLL should generate 40MHz for your 20bit data processing. At tx:The PLL should generate 800MHz internally to kick serial bit stream out at 800 Mbps. This fast clk is not accessible to you, it is for serdes use.

[Altera_Forum]

very clear explaination, thank you! 

I set the input clock frequency to 100MHz for both transmiter and receiver. than connected two input clock signals to a clock input pin. The Fitter merged the PLLs of Transmiter and Receiver.

[Altera_Forum]

I am still doubtful about your statement  

   --- Quote Start ---   than connected two input clock signals to a clock input pin.   --- Quote End ---     you only need one ref clk(driven by one signal)

[Altera_Forum]

Just like the following codes: 

module lvdsTransceiver(  input sysclk,  input reset,  input [19:0] txIn0,  input [19:0] txIn1,  input [19:0] txIn2,  input txIn_clk,    output [2:0] txOut,  output txOut_clk,    input rxIn0,  input rxIn1,  input rxIn2,  input rxIn_clk,  output [19:0] rxOut0,  output [19:0] rxOut1,  output [19:0] rxOut2,  output rxOut_clk0,  output rxOut_clk1,  output rxOut_clk2        );  lvdsTxr lvdsTxr_inst (  .pll_areset(reset),  .tx_in ( {txIn2,txIn1,txIn0} ),  .tx_inclock ( txIn_clk ),  .tx_coreclock ( ),  .tx_locked ( ),  .tx_out ( txOut ),  .tx_outclock ( txOut_clk )  );  lvdsRxr lvdsRxr_inst0 (  .pll_areset ( reset ),  .rx_in ( rxIn0 ),  .rx_inclock ( txIn_clk ),  .rx_locked ( ),  .rx_out ( rxOut0 ),  .rx_outclock ( rxOut_clk0 )  );   endmodule

[Altera_Forum]

What matters is using the right clock.  

It looks like you are not attempting to recover clk from data(CRD not used) but are provided with all the clks. So your loopback connection is ok.   The serial (fast clks) can be avoided by activating the CDR

[Altera_Forum]

how to activating the CDR?

[Altera_Forum]

Hi, 

 I should have said "use CDR". It is there for you in lvds instant. I believe - now - you may have misunderstood which clk is the ref clk for your internal PLL and which are parallel data clks   According to my experience with lvds(stratix II): The rxin_clk and txin_clk are the ref clks and have to be connected both to the ref frequency. There should be no serial data clk from or into the lvds. The lvds gives you parallel clks only. You will need these parallel clks on either side(tx/Rx) to clk your data into the lvds tx for serialisation and to read your desrialised data from the lvds rx.