How to use tri_state_bridge in sopc builder

[Altera_Forum]

I'm done of graphic images on the LCD and LCD character data on the same time (CYCLONE III DEVELOPMENT KIT). 

But when i complie the error message tells that the signals lcd_d_cn and lcd_wen are assigned twice, which isn't possible. some documents that need to make composite or tri_state to solve, but I do not know how.  My verilog program when i don't put tri state bridge into system as follows:  module bt4 (clkin_50, cpu_resetn, lcd_data, lcd_csn, lcd_d_cn, lcd_e_rdn, lcd_rstn, lcd_wen, lcd_en);  input clkin_50;  input cpu_resetn; inout [7:0]lcd_data; output lcd_csn; output lcd_d_cn; output lcd_e_rdn; output lcd_rstn; output lcd_wen; output lcd_en;  nios_sys DUT ( // 1) global signals: .clk_0(clkin_50), .reset_n(cpu_resetn),  // the_GLCD_CSN .out_port_from_the_GLCD_CSN(lcd_csn),  // the_GLCD_DATA .in_port_to_the_GLCD_DATA(lcd_data[7:0]), .out_port_from_the_GLCD_DATA(lcd_data[7:0]),  // the_GLCD_D_CN .out_port_from_the_GLCD_D_CN(lcd_d_cn),  // the_GLCD_E_RDN .out_port_from_the_GLCD_E_RDN(lcd_e_rdn),  // the_GLCD_RSTN .out_port_from_the_GLCD_RSTN(lcd_rstn),  // the_GLCD_WEN .out_port_from_the_GLCD_WEN(lcd_wen),   // the_lcd_0 .LCD_E_from_the_lcd_0(lcd_en), .LCD_RS_from_the_lcd_0(lcd_d_cn), .LCD_RW_from_the_lcd_0(lcd_wen), .LCD_data_to_and_from_the_lcd_0(lcd_data[7:0]) ) ; endmodule  when i put tri_state_bridge into system, the system have error as file "Doc1.doc" follows:   I hope anybody can help me! Thanks.

[Altera_Forum]

The error message is clear: you must connect something to the tristate bridge. Otherwise, what's the purpose of a bridge? 

Usually the TS bridge drives an external async device, such as sram or flash, so you need to add to the system the proper component and connect it to the TS master.

[Altera_Forum]

--- Quote Start ---  The error message is clear: you must connect something to the tristate bridge. Otherwise, what's the purpose of a bridge? Usually the TS bridge drives an external async device, such as sram or flash, so you need to add to the system the proper component and connect it to the TS master.  --- Quote End ---    I'm done of graphic images on the LCD and LCD character data on the same time (CYCLONE III DEVELOPMENT KIT). But when i complie the error message tells that the signals lcd_d_cn and lcd_wen are assigned twice, which isn't possible. some documents that need to make composite or tri_state to solve,so i use tri state bridge... if don't use tri state bridge,you can tell me others to slove.

[Altera_Forum]

The problem is that lcd_d_cn and lcd_wen signals are driven both by lcd_0 component and glcd_ pio ports. You can't do this. 

If your system must be capable to either, you must provide a method to select one group of signals or the other. Tristating signals (this doesn't mean using a tristate bridge!) could be a solution: you drive the signal only in the low state and tristate when not active; you then need a resistor to pull up to the high state. But I think in your case a simple logic port solution is better. Example:  nios_sys DUT ( ... .out_port_from_the_GLCD_WEN(lcd_wen1), ... .LCD_RW_from_the_lcd_0(lcd_wen2), ... ) ; assign lcd_wen = lcd_wen1 & lcd_wen2;  Same for other shared signals.