How to use up all cells in an FPGA?

Altera_Forum · ‎06-25-2009

I am going to be doing some radiation testing on an MAXII FPGA and I would like to program it with a fairly simple program that tells me when the FPGA has an upset. I would like the program to exercise most or all of the cells in the FPGA so that I can say whether or not the FPGA passed the testing with resonable certainty. I am not quite sure of a way to have a simple program use most of the space in an FPGA so I wanted to see if anyone had any input?? It would be much appreciated!!!

GR

Altera_Forum · ‎06-26-2009

MAX II has non-volatile (flash) configuration storage. Corruption of configuration memory would be the most likely radiation effect, but can be easily detected by a verify.

Regarding the suggested test, even if all logic elements are utilized in a design, the routing resources can't. So you can't achieve a 100% test anyway. Statistical considerations suggest however, that the significance of your test doesn't change much if you have 95% or 100% utilisation. Thus you should rather think about a test design that allows easy and complete verification of it's results rather than 100% utilisation.

Two identical LFSR with a comparison of both outputs can be starting point. You can add some arbitrary operations on the output numbers to fill up the logic array.

Altera_Forum · ‎06-26-2009

LFSR will do and another possible simple filler code is running several counters together then testing their equality.


type my_array is array(1 to 10) of integer range(0 to 255);
signal counter: my_array;
 
signal flag : std_logic_vector(9 downto 1);
......
process(reset,clk)
begin
if reset = '1' then
    counter <= (others => 0);
    flag <= (others => '0');
elsif rising_edge(clk) then
 
    for i in 1 to 10 loop
        counter(i) <= counter(i) + 1;
    end loop;
 
    for i in 1 to 9 loop
         if counter(i) = counter(i+1) then
             flag(i) <= '0';
         else
             flag(i) <= '1';
         end if;
    end loop;
 
end if;
end process;
 
alarm <= '1' when flag /= "000000000" else '0';--may need latching