Hi, everybody!
What I'm trying to do is to send some data to from FPGA to HPS over F2H bridge. I use my own Qsys component with MM slave and MM master interfaces. MM slave is connected to h2f master and MM master is connected to f2h slave. From Linux userspace program I send (over h2f) a start address for a memory region (data array) to FPGA and then I start a transaction from FPGA to HPS. I want to write 100 values to array. Since I use long long int (64 bits=8 bytes) array adress step is set to 8. It seems that everything goes right as from the oscillogram it can be seen that f2h asserts and deasserts waitrequest signal while write signal is high. Transaction takes about 3.7 microseconds (f2h clock is 100 MHz). But when I read array values in Linux application I get only zeroes.
Do I have to initialize FPGA-to-HPS bridge before I use it? If so, what registers must be set?
Do I form addresses correctly? I guess I can write data to SDRAM this way...
