I/O states in Cyclone III in JTAG mode

[Altera_Forum]

Hello all, 

 In Altera's application notes it is specified that during JTAG mode all I/O pins are tristated. It is sometimes mentioned that the weak pull ups are enabled when the I/O pins are tri-stated, for example after POR. In JTAG mode, are these internal weak pull ups enabled? Thank you, Boris.

[Altera_Forum]

If by "JTAG mode" you mean the period while you configure the FPGA through JTAG then yes, on recent FPGA famillies the I/O pins are tristated and the weak pull-ups are enabled.

[Altera_Forum]

Hi Daixiwen, 

By "JTAG MODE" I'm referring to the test state in which JTAG tests are being run on the Cyclone III chip. Does your answer cover this state? Thanks, Boris.

[Altera_Forum]

Weak-pullups are enabled depending on the configuration, if the device has been configured before activating BST mode. Otherwise inputs are high Z. Read the device handbook thoroughly, the question is answered therin.

[Altera_Forum]

Hi FvM, 

 In the hadbook it is mentioned that : "All user I/O pins are tri-stated during JTAG configuration. Table 9–15 lists the function of each JTAG pin."  I asked whether these pull ups are enabled after entering BIST mode. I don't see it in the handbook. It will be much appreciated if you tell me where I can find this information. Thank you, Boris.

[Altera_Forum]

Hi guys, 

Where can I find this description in the handbook ? Thank you, Boris.

[Altera_Forum]

The description is in the device handbook boundary scan chapter. 

 It's said, said the weak pull-ups are only active, if the fpga has been configured before activating bst mode for those pins that enable weak pull-up in the configuration.  I think that's pretty clear.

[Altera_Forum]

Hi FVM, 

 Sorry for being pain in the but but I searched for it here : www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf and I don't see it. What page is it on? Thanks again, Boris.

[Altera_Forum]

Altera preferred to omit the clearer description in previous device handbook versions. 

 Now the information is hidden in Note (1) to table 12-3:   --- Quote Start ---  Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.   --- Quote End ---    In previous versions, there was an explicite explanation of individual BST instructions affecting the IO states, e.g. for CLAMP:   --- Quote Start ---  If you are testing after configuring the device, the programmable weak pull-up resistor or the bus hold feature overrides the CLAMP value (the value stored in the update register of the boundary-scan cell) at the pin.   --- Quote End ---    In any case, if you are in doubt about the real device behaviour, why don't you simply try it?

[Altera_Forum]

Thank you FvM. Much appreciated.