Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

I am using an Arria 10 GX and cannot get any signals out of bank 2L, the 3V bank. I can move the signals to bank 2K at 1.8 V and they are fine. The VCCIO for bank 2L is at 2.98V on all three pins but the bank is acting as though it is not active while all

MBynu
Beginner
987 Views

of other bank are working fine. Is there a setting I am missing to activate bank 2L?

 

Thanks,

Mike

0 Kudos
1 Reply
YuanLi_S_Intel
Employee
873 Views

Hi Mike,

 

No special setting is required. Can you check if the VCCIO power rail is stable? Also, the 3V I/O Bank can use 3.0V and above I/O standard only.

 

Thank You.

0 Kudos
Reply