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Valued Contributor III
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I can't modify a file in quartus after generated the QSYS system? Please Help.

I'm making a flash controller in FPGA. I wrote the principal controller code, and another file that works like a test bench (a counter that generates the write and read instructions with datas) I named TOP. I want to connect both with avalon MM.  

 

So I open Qsys and create a system with a breach MM, a clock and a ip based on the controller code, then I click Generate . and exit, and in quartus I compile. 

 

Now I open Signal Tap II and create a stp project and save it, load the sof and load in the board, trigger the signal, and everything looks good  

 

Now comes the problem, I want to keep modifidying the controller code, because i want to test some values and different registers (debugg), the changes I do in the Quartus-II I compile them, and try to open signal tap ii and, then rapid compile again, load and trigger the system again, but the wave just show the same wave than before, no changes were done. The registers has the same old values. So It means I can't modify the file from Quartus. 

 

Then I go back to Quartus-II and, try to launch Qsys, I analize the file again and generate HDL. Compile and launch Signal tap again, with the same problem. but at this point I go back to Quartus-II it gives me this message, 

 

see Untitled 

 

https://alteraforum.com/forum/attachment.php?attachmentid=14734&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14734&stc=1  

https://alteraforum.com/forum/attachment.php?attachmentid=14734&stc=1  

https://alteraforum.com/forum/attachment.php?attachmentid=14734&stc=1  

 

It wants to change the file to the first version of the file (at the step of creating the qsys). So I dont know what to do now, any one has idea of what I'm doing wrong. Really thanks in advance to everyone.
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Valued Contributor III
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I just realize the QSYS must be not the problem. If I modify a file originating the custom logic in qsys, I just have to generate the HDL from QSYS again and consequently the file inside the QSYS .qip keep the changes.  

 

The problem seems to be in the Logic Tap II analyzer. I can only see the wave belonging to the original file which I first created the .stp file, but now, no matter if I create a new STP file and delete the old STP file, when I run the Signal Tap and trigger, it still show me the old version of the verilog code. So, I'm guessing the problem is that Signal Tap II is addressing to a kind of internal "backup" of the original file (which technically does not exist anymore because I made the changes) but it does not show me the modified file wave as I wish. 

 

Ommit the message in the attached image, that's not the problem anymore, problem arise only in the signal tap II, because it does not show me the modified wave. 

 

 

Any ideas?
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Valued Contributor III
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QSYS makes a copy of all the hdl files when you generate the hdl, so you are right that each time you modify your HDL files you need to regenerate the QSYS system before compiling the project again. Or you edit the copies, but you risk getting them overwritten the next time you click generate. 

There is no "back-up" of the project for signal tap, as long as you make sure that the QSYS system has been regenerated, this is what will be in the FPGA and what you will see in signaltap. What you can see is the waves from the previous run, if you saved a signaltap file with data. But as soon as you click "run analysis", it will be overwritten with new data. 

 

After you compiled the project you can use the RTL viewer to check that your code modifications have been implemented by Quartus. (and generally the RTL viewer is great when you need to check that Quartus understood what you meant in your code).
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--- Quote Start ---  

QSYS makes a copy of all the hdl files when you generate the hdl, so you are right that each time you modify your HDL files you need to regenerate the QSYS system before compiling the project again. Or you edit the copies, but you risk getting them overwritten the next time you click generate. 

There is no "back-up" of the project for signal tap, as long as you make sure that the QSYS system has been regenerated, this is what will be in the FPGA and what you will see in signaltap. What you can see is the waves from the previous run, if you saved a signaltap file with data. But as soon as you click "run analysis", it will be overwritten with new data. 

 

After you compiled the project you can use the RTL viewer to check that your code modifications have been implemented by Quartus. (and generally the RTL viewer is great when you need to check that Quartus understood what you meant in your code). 

--- Quote End ---  

 

 

Thanks Daixiwen, I did as you said, after made changes in Quartus, I regenerated in QSYS. Consequently changes are made in the submodule of the .qip project. However the Signal Tap II keeps showing me the old values I inserted previously, this is, the previous version of the verilog file. 

 

I don't get why. It is possible that the problem is in the TCL addressing a old version of the file? or that I have to set the Signal Tap to refresh the screen with the new values of the file??
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Valued Contributor III
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What do you mean by "showing me the old values"? The signal names, or is it that when you look at the waves it seems that it is still the old logic that is in place? 

If it is just the signal names, the ones that are not part of your design any more are shown in red, and you need manually to delete them and insert the new signals in the window. 

If it is just the wave that looks the same, did you click again on "run analysis"? If you still see what looks like the old logic would generate, then it means that either your modified code wasn't used by quartus, or that it doesn't do what you think it did. In either case check with the RTL viewer what Quartus synthesized.
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Valued Contributor III
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--- Quote Start ---  

What do you mean by "showing me the old values"? The signal names, or is it that when you look at the waves it seems that it is still the old logic that is in place? 

If it is just the signal names, the ones that are not part of your design any more are shown in red, and you need manually to delete them and insert the new signals in the window. 

If it is just the wave that looks the same, did you click again on "run analysis"? If you still see what looks like the old logic would generate, then it means that either your modified code wasn't used by quartus, or that it doesn't do what you think it did. In either case check with the RTL viewer what Quartus synthesized. 

--- Quote End ---  

 

 

I just opened the RTL viewer, I found out that after compilation the RTL viewer can update the name of the register (for example I modified from "comm_in" to "comm_in_test" and changed the value, The logic Tap II also update the name of the same register (it turns red the old register name "comm_in", so I delete and add a new node from the list: "comm_in_test"). Here gets crazy, the value of that register "comm_in_test" is the old value from "comm_in", I don't even understand where the system gets that value since it comes from a parameter, which I actually changed to a new number... 

 

Going back to Quartus I added a simple logic and a register like this: 

 

/////////////////////////////////////////////// 

parameter test_A = 8'b0001_1111; 

 

reg [7:0] test_reg; 

 

always@ (posedge clock_sink_clk or negedge reset_sink_reset) begin 

if (~reset_sink_reset) 

test_reg <= 0; 

else  

test_reg <= test_A; 

end 

 

//////////////////////////////////////////// 

 

Compiled and generated in qsys, I checked and the submodule of qsys has made the changes also. 

 

Then I open the RTL viewer, I cannot find the new register in the design, RTL viewer did not register the new logic I added.  

 

What do you think is happening, this problem is a real puzzle. 

 

I'm including the files I'm using in verilog. The TOP file generate the signals for the flash controller file itself.
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Valued Contributor III
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If your test_reg register is not used in the design (i.e. not connected to a FPGA pin or used by another module to generate a signal on an FPGA pin) then the whole register will be optimized away by the quartus synthesizer. You should see a warning about this in the synthesizer log.

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