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Dear all,

Please help me out her. counter <= counter + '1'; this is my instruction this is my error. So what is the mistake in it? Error (10327): VHDL error at led_blink.vhd(24): can't determine definition of operator ""+"" -- found 0 possible definitionsLink Copied

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Thats because you havent defined a "+" function, or havent included a package that defines a "+" function that can add together whatever the type of counter is and '1' (which I assume you expect to be a std_logic)

Why not include all the code, not just a single line, as it all depends on what libraries you have included and what type counter is.- Mark as New
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Hi,

To use mathematical operators , you need to include the arith library package. I've included the list of packages in the IEEE library. You have to include the respective package for the operations you want to use. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_textio.all; use IEEE.std_logic_arith.all; use IEEE.numeric_bit.all; use IEEE.numeric_std.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; use IEEE.math_real.all; use IEEE.math_complex.all; Hope this helps.- Mark as New
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you might want to think about converting your signal to (un)signed, then you can use +

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--- Quote Start --- Dear all, Please help me out her. counter <= counter + '1'; this is my instruction this is my error. So what is the mistake in it? Error (10327): VHDL error at led_blink.vhd(24): can't determine definition of operator ""+"" -- found 0 possible definitions --- Quote End --- To use "+" operator. you need to include library package. While including library consider following points. 1."use IEEE.std_logic_unsigned.all" in your code with "library IEEE & use IEEE.std_logic_1164.all". Your problem will be solved. 2.Can't use both"signed and unsigned" library together for your counter design. Error will remains. 3.If you use "use IEEE.std_logic_signed.all" in your code with "library IEEE & use IEEE.std_logic_1164.all". Your problem will be solved. Find the image for more details. https://www.alteraforum.com/forum/attachment.php?attachmentid=14264 https://www.alteraforum.com/forum/attachment.php?attachmentid=14265 https://www.alteraforum.com/forum/attachment.php?attachmentid=14266 https://www.alteraforum.com/forum/attachment.php?attachmentid=14267 Best Regards, Tzi Khang, Lim (This message was posted on behalf of Intel Corporation)

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No

No No This is bad advice. Never use IEEE.std_logic_unsigned.all or IEEE.std_logic_signed.all. Those are non standard libraries, and cause a variety of problems, especially the day where you will need to use both signed and unsigned values in the same module. Only use those two packages: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Then change the type of the signal counter to wither "signed" or "unsigned", depending on what you want, and then you can just use`counter <= counter + 1;`

If you never need the actual bit representation of the signal counter you can also make it a natural or an integer. Just remember to put a fixed range on it.
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--- Quote Start --- No No No This is bad advice. Never use IEEE.std_logic_unsigned.all or IEEE.std_logic_signed.all. Those are non standard libraries, and cause a variety of problems, especially the day where you will need to use both signed and unsigned values in the same module. Only use those two packages: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Then change the type of the signal counter to wither "signed" or "unsigned", depending on what you want, and then you can just use

`counter <= counter + 1;`

If you never need the actual bit representation of the signal counter you can also make it a natural or an integer. Just remember to put a fixed range on it. --- Quote End --- NO STILL CODE WILL HAVE SAME PROBLEM. with library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Please correct me if i am wrong. i'm using QuartusII 17.0 ------------------------------------ -- Quartus Prime VHDL Template -- Basic Shift Register library ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std.all; entity cnt is port ( clk : in std_logic; enable : in std_logic; sr_out : out std_logic_vector(3 downto 0); sr_in : in std_logic ); end entity; architecture rtl of cnt is -- Build an array type for the shift register signal sr: std_logic_vector(3 downto 0); -- Declare the shift register signal begin process (clk) begin if (rising_edge(clk)) then if (enable = '1') then sr<=sr+'1'; end if; end if; end process; -- Capture the data from the last stage, before it is lost sr_out <= sr; end rtl; ------------------------------------------------------------------------- ERROR message Error (10327): VHDL error at cnt.vhd(36): can't determine definition of operator ""+"" -- found 0 possible definitions Error: Quartus Prime Analysis & Elaboration was unsuccessful. 1 error, 3 warnings Error: Peak virtual memory: 742 megabytes Error: Processing ended: Thu Nov 02 23:28:17 2017 Error: Elapsed time: 00:01:02 Error: Total CPU time (on all processors): 00:00:41 I think Representative is correct.
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your problem is unrelated to addition (which requires unsigned type if still want to add 1). your shift should shift input bit through 4 stages:

on the clk edge: sr <= sr(2 downto 0) & sr_in;- Mark as New
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--- Quote Start --- I think Representative is correct. --- Quote End --- He is correct, if code is left as is. But Daixiwen is making the point that std_logic_(un)signed are not part of the VHDL standard, although they are supported by Quartus (and pretty much all tools). Using std_logic_unsigned goes against the spirit of VHDL. If the user wants to switch to numeric std, then the code would need to be: sr<=sr+1;

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```
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cnt is
port
(
clk : in std_logic;
enable : in std_logic;
sr_out : out std_logic_vector(3 downto 0);
sr_in : in std_logic
);
end entity;
architecture rtl of cnt is
-- Build an array type for the shift register
signal sr: unsigned(3 downto 0);
-- Declare the shift register signal
begin
process (clk)
begin
if (rising_edge(clk)) then
if (enable = '1') then
sr<=sr+1;
end if;
end if;
end process;
-- Capture the data from the last stage, before it is lost
sr_out <= std_logic_vector(sr);
end rtl;
```

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--- Quote Start --- I think Representative is correct. --- Quote End --- I didn't say he wasn't correct, I said it was bad advice ;)

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Hi

Thank you Daixiwen & Tricky. Yes you are right.i Could have added reset. it's only for checking the the library so only i have not concentrated on code/logic. Thanks.- Subscribe to RSS Feed
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