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I need yor hlp.....

Altera_Forum
Honored Contributor II
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Hello!!! 

this code for the first component of QPSK modulator(serial to parellel converter.the second compnent is NRZ,i need to know how can I integrate the output of serial to parellel with NRZ. 

this code of(s to p):  

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use IEEE.STD_LOGIC_ARITH.ALL; 

use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity FFF is 

Port ( S : out bit; 

R : in bit; 

clk : in bit; 

P : in bit_vector (7 downto 0)); 

end FFF; 

architecture Behavioral of FFF is 

--signal shift_reg : std_logic_vector(7 downto 0); 

begin 

process (clk,R,P) 

variable shift_reg : bit_VECTOR(7 downto 0); 

begin 

if R ='0' then 

shift_reg(7 downto 0) := P(7 downto 0); 

elsif (clk'event and clk='1') then 

S <= shift_reg(7); 

--shift_reg (7 downto 1) := shift_reg(6 downto 0); 

shift_reg (7 downto 0) := ( shift_reg (6 downto 0) & shift_reg(7) ); 

end if;  

end process;  

end Behavioral; 

this code for NRZ:----------------UNIPOLAR TO BIPOLAR---------------[LOGIC 0=-1, LOGIC 1=1]------- 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

USE ieee.std_logic_unsigned.all; 

USE ieee.std_logic_signed.all; 

USE ieee.numeric_std.all; 

 

------------------defines two types: unsigned and signed 

 

ENTITY unipolar_bipolar IS 

 

PORT( 

in_i,in_q : IN std_logic_vector (3 downto 0); -------4 bit------- 

bI,bQ: OUT std_logic_vector (3 downto 0) -------4 bit------- 

); 

END unipolar_bipolar ; 

 

 

ARCHITECTURE beh OF unipolar_bipolar IS 

 

signal p: integer;------------out 

signal k: integer;-------------in 

signal n: std_logic_vector(3 downto 0);--------------out(final) 

signal i:integer; -----------------------for loop 0 until 3 (4 bit)----------- 

 

begin 

 

for i=> '0'; 

LOOP 

i=n; 

when in_i(n)=> k & in_q(n)=> k then 

 

case k is 

 

when k ='0' then -----must invert to signed value---[-1] 

p <= '1'; -------in std_logic 

 

out_q(n)<= conv_integer(p); 

out_i(n) <= conv_integer(p); --------convert into integer(signed) 

 

end case; 

 

 

case k is 

 

when k ='1' then-----must invert to unsigned value--[1]  

p <= '1'; -------in std_logic 

 

out_q(n)<= conv_integer('0'& p); 

out_i(n) <= conv_integer('0' & p); --------convert into integer(unsigned) 

 

end case; 

 

n = i+1; 

when n='3' loop; 

end LOOP; 

end beh; 

 

I hope help me as soon as possible:confused: :confused: :confused:
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