02-22-2019 08:48 PM
I am using Cyclone IV GX FPGA
- Does the flash should have specific feature to be able to use as memory for different configuration file? or just meeting the minimum required memory is the only condition?
- can Quartus handle programming the flash with more than one configuration file easily?
- is the core mentioned in Altera documents easy to use and how big is? can that handle easily choosing the right configuration file just through the address?
- should I consider any specific note during circuit design?
02-25-2019 07:15 AM
Hello HT, 1. Usually for PS configuration, we recommend to user to follow the supported flash memory devices for FPL IP. You may refer to the supported flash memory devices for PFL IP in the following link (Table 1 and 2 on page 4): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf#page=4 2. Yes, you can program more than one configuration file into the flash. Quartus can handle it properly. 3. Basically, you need to have Parallel Flash Loader (PFL) IP to control configuration from the flash device. And the fpga_pgm[ ] pin signal is used to determine the page for the configuration. You may refer to the information the PFL IP core input and output signals in the Table 17 (on page 41) https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf#page=41 4. You may refer to the PFL IP user guide and Cyclone IV pin connection guide during circuit design. PFL = https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf Pin connection = https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv/pcg-01008.pdf Thanks.
03-01-2019 01:07 AM