I2C slave in Cyclone II device

[Altera_Forum]

Hi, 

 I have written a simple I2C slave receiver in vhdl that I want to put in a cyclone II device. It is asynchronous and detects start and stops and device address + Rd/Wr and subadress. If both the device and sub address are correct then the databyte will be accepted. It looks good when I simulate it but I get problems when I put it in HW. I use a microprocessor on another PCB as a Master I2C. I runs at 200KHz. My slave in the FPGA ACK:s the way it should after both the device and subaddress. BUT, when it comes to the transfer of the databyte it goes all wrong! After the 7:th I2C clockpulse the clockgeneration stops and the SDA line are pulled LOW. I have 2 DVI circuits on the same board as the FPGA and this circuits is easaly configured. I know this is a asynchronous construction but it seems to work on the two first bytes. Is there anyone experienced a problem like mine?  Thank You!

[Altera_Forum]

There may be a particular timing problem with your asynchronous processing or a problem with the SCL waveform, that possibly causes double clocking at the edges. Generally you'll hardly achieve the specified glitch tolerance for the I2C lines with an asynchronous design without external signal filtering and schmitt-trigger gates. It would be much more simple to do it synchronously with a clock.

[Altera_Forum]

Hi, 

 okay. I just want to do some test by sending some panel data from a panelboard to my FPGA. Later on I will try to write a good, synchronized I2C slave with buffers and all that stuff. But for know do you think it would work if I implement some sort of glitch filter in my FPGA? If this is so, should I filter only the SCL line or the SDA line as well? If the SCL freq. is 200Khz, what sampling freq. should I need on my glitch filter?  Thank You!

[Altera_Forum]

--- Quote Start ---  what sampling freq. should I need on my glitch filter?  --- Quote End ---   You can e.g.refer to the tsp value of 50 ns in the Philips/NXP I2C bus specification. But if you implement a clocked glitch filter, why not completely switch to a synchronous design, which has a much more straightforward timing scheme?   To prevent from a false start condition, SDA should be filtered, too. Although a false start would be followed by a stop automatically and thus can't do much harm.

[Altera_Forum]

Hi, 

 a glitch filter on the SCL line seems to work just fine! At least I can send some bytes now.:) I used a internal clk and set the FILTER_LENGTH to 3 so spikes shorter than three oscillator periods are filtered out.   Thanks, nice talking to You!