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hi everybody,
I have another one problem in generating a system in sopc . here is my procedure. With the class.ptf file in the address below: http://users.ece.gatech.edu/~hamblen/de2/d...logic_open_i2c/ I create a new component . there is a error in generating the system. there it is: # ############## Perlcopy: cannot open source file C:/User/shalom/vhdl/i2c_master/hdl/i2c_master_bit_ctrl.v: No such file or directory at c:/altera/70/quartus/sopc_builder/bin/filename_utils.pm line 182. Error: Generator program for module 'i2c_master_0' did NOT run successfully. generator cmd was 'c:/altera/70/quartus//bin/perl/bin/perl # ############## thanks by advance of the helpLink Copied
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sorry , i don't know why but the address in the previous topic is wrong.
the correct address is: http://users.ece.gatech.edu/~hamblen/de2/de2_demonstrations/de2_net/user_logic_open_i2c/ thanks.- Mark as New
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i used the file download from the address you offord above //users.ece.gatech.edu/~hamblen...ogic_Open_I2C/,
a system in sopc can generated with no error. but the component is of a WishBone bus. how to modify to a component of Avalon bus?- Mark as New
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If you don't need heavy traffic on the i2c, it would be easier to use bidirectional pio or gpio to control the i2c bus and do it with bit-banging software. Almost every PC uses bit-banging i2c.
- Hippo- Mark as New
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now i use the i2c ip core downloaded from opencores.org, by VHDL.
build it in SOPC, following some trainings.- Mark as New
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hello,
what is the differents training, because when I create the Component I2C from open core i have some errors and I don't know how to resolve it? thanks- Mark as New
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--- Quote Start --- now i use the i2c ip core downloaded from opencores.org, by VHDL. build it in SOPC, following some trainings. --- Quote End --- HI, i am very new to all this and right now working on a project with main task of integrating I2C bus in cyclone ii. The ip core to be used is same as from opencores.org. Can you tell me how you built it in SOPC? thanks D

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