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I have been getting Linux up and running on a Cyclone III. Overall, things were going smoothly. I got the reference design running, added an extra UART and some GPIO and everything came together right away.
Now, I am trying to get I2C (and eventually SMBus) working. I am perfectly happy to use the GPIO bit-bang method for now as described here: http://www.nioswiki.com/gpio Unfortunately, I can't get the communication to happen. I am using pins 10 and 11 in my GPIO block. When I configure them as outputs, I can toggle them from software without an issue so I know things are connected right. I believe I have added most of the things correctly to config.c. I see this when I boot.
i2c /dev entries driver
i2c-gpio i2c-gpio.0: using pins 10 (SDA) and 11 (SCL)
However, when I run 'i2cdetect 0', no devices are detected. I put a 'printk' in the gpio_set_value() and I see that the gpio/i2c driver trying to toggle the correct pins. However, I can't detect any devices. I haven't even seen the scope move (although I should probably try this again.) Here is my code from config.c:
static struct i2c_gpio_platform_data i2c_gpio_0_data = {
.sda_pin = 10,
.scl_pin = 11,
.sda_is_open_drain = 1,
.scl_is_open_drain = 1,
.scl_is_output_only = 0,
.udelay = 5,
};
1. Does anyone know where I else I might have something wrong? I can't find much more documentation. I tried to follow everything described in the NEEK-based design on the NIOS wiki that I linked to above. 2. Should I just use the opencores module? Can I easily plug onto the Avalon bus in SOPC builder? (I'm pretty green on the whole FPGA/verilog stuff. I am a software guy.) 3. Is the udelay the length of one transition or two? In other words, will the frequency for udelay = 5 be 200 khz? Thanks in advance, Dave ...
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I think I figured out my own problem. I had been using the PIO peripheral provided by Altera with SOPC Builder. I needed to download the Linux-specific gpio block from the ip library that is on the nioswiki. It has a completely different register map that is more amenable to bit-banging. (It uses one register to handle all the functions for each GPIO pin, not one register that handles a single function for up to 32 pins.)
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