I2S receiver in FPGA

[Altera_Forum]

Hi, i am working on a bachelor project where i amongst other things want to receive data from some ADC's to a NIOS processor on the de2-115 board (cyclone 3). the ADC's transmits over I2s lines where they are the masters. i am currently trying to figure out how to implement the slave-receiver. 

 I initially wanted to implement the receiver in vhdl, but someone told me that would take several months, so now i am doing some more research. is it true that this is a big job? it seems to me from the I2S specifications that it is little more than a shift-register, plus som logic to put the data in a fifo.  i have also come over the an487 reference design, where a SPI interface is bridged, and used to send data to a I2s slave.  could i do this the other way around using the SPI interface IP-core from altera. Either configure the SPI interface to receive directly from the ADC (not much faith in this) or implementing a simple bridge(if that is the correct term)? as i understand I2S and SPI is not totally different.  Appreciate any help and tips.

[Altera_Forum]

It could be done in less than a day, even a couple of hours, for an 'experienced' VHDL engineer, a novice would take of course longer but not months, even if you are a beginner in VHDL. As you indicate the 'suggestion' schematic in the i2s specification (www.nxp.com/acrobat_download2/various/i2sbus.pdf) doesn't look that difficult.  

I don't see much relevance in AN487 though. Converting an I2S into a SPI doesn't really make sense I'd say. What ADC(s) are you using?

[Altera_Forum]

Thanks, as you probably figured out im not particulary experienced with this but ive had a few courses.  

 I will be using two or more TI PCM4204 ADC's (not allowed to link)

[Altera_Forum]

okay, i think i made it. i wrote some vhdl that simulates right from what i can read from the ADC datasheet. 

Thanks