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Altera_Forum
Honored Contributor I
1,572 Views

IP generated by Intel HLS Compiler is Missing Module IP in Platform Designer (Qsys)

Hi,  

 

Sorry for my poor English!!!:oops: 

-- 

 

Intel HLS Compiler (i++) can generate IP component for Platform Designer. 

I can make IP component by i++. 

 

I make my project in Quartus Prime and open Platform Designer. 

 

Next I select "IP Catalog / Generic Component" to use i++ components.  

I select "xxx.ip" file generated by i++. 

But IP generated is Missing IP.  

 

And display  

"Error: xxx.xxxx_internal_inst: Component xxxx_internal 1.0 not found or could not be instantiated" :mad: 

in Parameters Parametarization Message. 

 

why ?:( 

 

thanks to read.
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3 Replies
Altera_Forum
Honored Contributor I
214 Views

You don't mention it, but did you set the Generic Component's instantiation type to HLS and then click Import to import the .ip file? You can't leave the instantiation type as IP.

Altera_Forum
Honored Contributor I
214 Views

thanks for reply ! 

 

I know Genreric Component's instantiation type to HLS, but I made IP by i++ in console. If using Generic Component's instantiaion type to HLS for use i++ IP in Qsys, we must regeneric IP one more. 

 

otherwise Is i++ in console for verify and simulation ?
Altera_Forum
Honored Contributor I
214 Views

Are you able to see the IP you created using HLS? 

From what I know we go to tools -> options and update the 'Quartus project IP search path' to where our IP is located. 

This then will update the path and show your IP in the 'Existing IP variants' section. 

From here it is easy to add your IP. 

 

Hope this helps. 

 

-Saumil
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