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FResc
Beginner
1,011 Views

Implementation of a custom streaming sink for the Modular ADC Core on a MAX10M08 Ev Kit not working. Any idea why?

I'm trying to implement a custom IP as a streaming sink for the modular ADC core, showing the actaul converted data on the LEDs of the MAX10M08 Ev Kit.

Somehow I am unable read out the data in the custom IP core. With the ADC Toolkit I am able to check, that the ADC is up and running. With the RTL Viewer I am able to see, that the ADC core is wired correctly togther. But I'm not able to display any data, no matter whatever I'm trying.

Does anybody has a some advice/hint?

 

Below you'll find the code of my custom IP:

 

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

 

ENTITY led_st_sink IS

   PORT(

      csi_clk                   : IN   std_logic;

      rsi_reset_n               : IN   std_logic;

 

      avm_csr_address            : OUT   std_logic_vector(2 downto 0);

      avm_csr_read            : OUT   std_logic;

      avm_csr_write            : OUT   std_logic;

      avm_csr_writedata         : OUT   std_logic_vector(31 downto 0);

      avm_csr_readdata         : IN   std_logic_vector(31 downto 0);

      avm_csr_waitrequest         : IN   std_logic;

 

      asi_adc_valid              : IN   std_logic;

      asi_adc_channel         : IN   std_logic_vector(4 downto 0);

      asi_adc_data            : IN   std_logic_vector(11 downto 0);

      asi_adc_startofpacket      : IN   std_logic;

      asi_adc_endofpacket      : IN   std_logic;

 

      coe_led                  : OUT   std_logic_vector(4 downto 0)

   );

END led_st_sink;

 

ARCHITECTURE rtl of led_st_sink IS

SIGNAL   adc_run : std_logic;

BEGIN

   adc_start : PROCESS(csi_clk, rsi_reset_n)

   BEGIN

      IF rsi_reset_n = '0' THEN

         adc_run <= '0';

         avm_csr_address <= "000";

         avm_csr_read <= '0';

         avm_csr_write <= '0';

         avm_csr_writedata <= x"00000000";

      ELSIF rising_edge(csi_clk) THEN

         IF adc_run = '0' THEN

            avm_csr_write <= '1';

            avm_csr_writedata <= x"00000001";

         ELSE

            avm_csr_write <= '0';

            avm_csr_writedata <= x"00000000";

         END IF;

      END IF;

   END PROCESS adc_start;

 

   adc_st_read : PROCESS(csi_clk, rsi_reset_n)

   BEGIN

      IF rsi_reset_n = '0' THEN

         coe_led <= "00000";

      ELSIF rising_edge(csi_clk) THEN

         IF asi_adc_valid = '1' THEN

            coe_led <= asi_adc_data(11 downto 7);

         END IF;

      END IF;

   END PROCESS adc_st_read;

END ARCHITECTURE rtl;

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4 Replies
JonWay_C_Intel
Employee
8 Views

Hi @FResc​ 

 

Could you perform a simulation to make sure the custom RTL is working? Or run some signaltap to see which part of your code is not working as expected.

 

You might also want to refer to https://www.m-pression.com/solutions/boards/odyssey/personality-5

Refer to RTL code that converts the ADC level to LED. From there when you are sure your RTL is working, wrap it up as custom Qsys component.

 

Abe
Valued Contributor II
8 Views

Your code has some flaws.. for starters, the signal adc_run is assigned '0' in the first process on the assertion of reset, but after this in the clock loop, is checked if it is '0' and not assigned any other value. This will infer latches for this signal. Plus, the signal will always be assigned to '0' and will never change, making the else part of the code unreachable. You should assign the signal in the process and use it in the another process to prevent latch inference.

 

The same goes for the avm_csr_read and avm_csr_address signals. Correct the code, run a functional simulation, and also check the synthesis report after compilation.

 

FResc
Beginner
8 Views

Hello JwChin and Abe

Thanks for your hints. Adapting my code accordingly the Odyssey example showed first positive results (response streaming sink and sequencer MM master in the top entity, only PLL and ADC in the QSYS). From there on I continued my investigations.

I've figured out, that my streaming sink did not fully match the streaming source of the ADC IP, and therefore QSYS added an auto-inserted ST adapter. This adapter did not pass through the valid signal. After completely matching all signals, witdh, bits per symbol, max. nr. of channels, ... QSYS did not add any adapter anymore and everthing startet to work as it should.

Concerning the flaws in my code: They will of course be all corrected as soon as I'm starting to implement the real intended function of my custom IP. First goal is now reached, the ADC core is successfully connected.

JonWay_C_Intel
Employee
8 Views

@FResc​ 

 

Glad to hear that it all worked out!!