Implementing LVDS transmitter in altera EP4CGX15 - Basic information

[Altera_Forum]

Hello all - 

  I am a beginner implementing LVDS transmitter on a EP4CGX15 device with 4 data pairs and 1 clock pair. The data sheet tells me that bank 5 and 6 can generate true LVDS without the need for the extra resistors used in emulated LVDS. So I was going to use the IOs in bank 6.   I want to get things cleared so that I don't have to spin the board more than once.   Questions 1) Looks like ALTLVDS can be used to generate the necessary signals. I have chosen 4 diffio pairs for the data part. Say DIFFIO_(R1,R2,R3,R4) . Is this a valid assignment ? 2) Which type of pins can I use for clk pair output of the lvds . ( PLL_CLKOUT ? It seems DIFFCLKx pins are input pins.)  3) Does ALTLVDS generate the necessary clock output automatically based on my input specifications ? what is the reference clock it uses to generate it from ? 4) Generally does altera fpga need a XTAL to feed its reference clock(general chip functioning) or it can generate it within itself ?   Appreciate if anybody can answer these questions.   Thanks JP

[Altera_Forum]

The best way to answer some of your questions is to put together a sample project and run it through Quartus. Bank 6 looks like a good choice, allowing you to drive True LVDS. 

 1) Yes, ALTLVDS_TX is the primitive to use to drive LVDS signals from the FPGA. Providing you've chosen DIFFIO pins then you should be OK. However, if you're assigning any other single ended signals in the vicinity of these LVDS signals, Quartus may well complain about cross talk and not fit your design.  2) Yes, PLL_CLKOUT will drive a clock out of the FPGA. Those pins have the added advantage that the source of that clock can be from a PLL. (DIFFCLK pins are input only).  3) The ALTLVDS_TX primitive will generate a clock, synchronous to (and a frequency multiple of) the data generated from the same primitive, if you select that option when configuring it. You will be able to route this clock out of the device.  4) Yes you will need an external oscillator for the FPGA. It doesn't have an internal one (except for configuration and you can't use it).  Put together a simple project instantiating the primitives discussed, run it through Quartus and it'll let you know whether it's happy or not.

[Altera_Forum]

Thanks a_x_h_75. That answers almost all of my questions. 

1) If I configure ALTLVDS_TX to generate a clock from the same primitive then I should route the output clock to the available DIFFIO pins in that bank rather than the PLLCLKOUT pins. Is that right ?  2) The XO crystal feeding clock can be connected to the global CLKx input pins in the intended bank. Is that right ?  Appreciate your time.

[Altera_Forum]

1) Yes. The PLLCLKOUT function those pins offer is reserved for direct, low jitter output paths from the PLLs. You might (although I suspect you won't) be able to route the ALTLVDS_TX generated clock to the PLLCLKOUT pins only by virtue of the fact they are also general purpose I/O pins. However, they don't explicitly state those pins support differential I/O, except when used for their PLLCLKOUT function. 

 2) No, not really. Your chosen bank may or may not have dedicated CLKx pins. Feed the XO output clock into a CLKx pin in a bank powered at the appropriate voltage for the XO. Quartus will be able to use a CLKx signal throughout the device, not just in the bank it feeds.  Regards, Alex

[Altera_Forum]

Thanks Alex for answering my questions.