First of all if you want to implement your PID in an FPGA, and presumably you will, otherwise AlteraForum.com is not your best forum, then you can not avoid time discrete sampling. The FPGA is a digital processor, not analogue.
Second, by using sufficient high sample rate, and here the FPGA is first class, you can make it work as was it a time continous system.
If your loop has very high bandwidth you have to be careful not to introduce excessive delay in you ADC,DAC and FPGA. So choose your ADC,DAC carefully with latency in mind in addition to number of bits and
monotonic response and
low differential non linearity, as well. The latter is important as you may otherwise hit zones where the loopgain changes amplitude and even get phase reversals (ouch)!
PID algorithms can be made in a few clock cycles, so the latency here is given by clock frequency mainly.
Note that for instance an FIR filter has a delay which is N/2 where N is the number of taps, which can easily up to 100, typically posing problems in a closed loop.
If you need filtering then an IIR filter is better. In fact the PID is an IIR filter.
