Since the LVDS SERDES Ip has one constraint: all the RX channel should be placed in one IO bank, which has 24 RX channels in max, and they can only be clocked by the IO PLL resides in that IO bank.
If the RX channel num is larger than 24, than cannot use the LVDS SERDES directly, how to do it then? User an external clock buffer chip to distribute the clock to 2 LVDS clocks, than divice the 40 RX into two groups?
