Increase ADC resolution

[Altera_Forum]

Hi 

 I'm new to FPGA's. I need to increase the resolution of an 8bit 40Msps ADC through oversampling. I would just like to know if it is possible to implement this on a cycloneII. If anyone also knows how to go or give me tips on how to increase the resolution through decimation that would be of great assistance.  Thank you.:)

[Altera_Forum]

http://www.rane.com/note137.html

[Altera_Forum]

This is farly easy to do with altera's FIR compiler. You start the megawizard and selects your architecture, decimation rate and it basically generates the filter for you. The most difficult part is, I would say, scaling of the result and interfacing to your adc, in particluar if it is not a parallel port adc. Be careful with timing on the adc port. It is very easy to get timing violations which only will show up in real hardware.

[Altera_Forum]

If your oversampling frequency is high (i.e. at least 1 order of magnitude higher than the sampled signal) and decimation rate low (i.e. low number of added resolution bits), you can use a simple adder to solve the problem. Example: 8bit ADC, want 10bit ADC (2 bits added resolution) -> you need to add each 2^2=4 samples and use the result as your 10bit output. For 12bit output, you would have to add batches of 2^4=16 samples, and so on. 

 For lower oversampling frequencies you will have to use a weighted adder instead (do a search for 'exponential average' if you don't know what is that).  Getting your hands dirty with DSP stuff is fun :)

[Altera_Forum]

--- Quote Start ---  If your oversampling frequency is high (i.e. at least 1 order of magnitude higher than the sampled signal) and decimation rate low (i.e. low number of added resolution bits), you can use a simple adder to solve the problem. Example: 8bit ADC, want 10bit ADC (2 bits added resolution) -> you need to add each 2^2=4 samples and use the result as your 10bit output. For 12bit output, you would have to add batches of 2^4=16 samples, and so on.  For lower oversampling frequencies you will have to use a weighted adder instead (do a search for 'exponential average' if you don't know what is that).   --- Quote End ---   All of this is in fact included if you design using the Altera FIR megawizard. It does the tedious work of construction of the adder network, and puts weights on the taps and calculates the frequency response as well!. The "exponential averager", "weighted averager", "running averager" etc. are simply FIR filters with specific tap values. In FIR compiler you can load tap-values (coefficient values ) from a simple text file if you are not content with the automatically generated values.   --- Quote Start ---  Getting your hands dirty with DSP stuff is fun   --- Quote End ---   Yes, and the right tool makes it even more fun!