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Independent clock mode True Dual port RAM in Agilex

AlteraUsr
Beginner
534 Views

I need to use a true dual port RAM with separate clock for each port. This used to be possible in Arria 10 (where M20K was used), but in Agilex, I see that apart from required number of M20Ks, a whole lot of ALMs are used for the dcfifo inside a fifo_wrapper module. I think it is achieved through emulated True Dual Port mode.  My memory being huge (64K deep and 10 bit wide), it is taking ~60K ALM for the FIFO wrapper which is an overhead when I migrate my design to Agilex.

Is this expected? Why is Agilex, being a latest family, not supporting a feature seen in Arria10.

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8 Replies
Nurina
Employee
513 Views

Hi,


Agilex does support Independent Clock Mode: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/ug-ag-memory.pdf#...


Did you try regenerating the RAM IP?


Regards,

Nurina


Nurina
Employee
487 Views

Hi,


Any updates?



Nurina
Employee
471 Views

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!

AlteraUsr
Beginner
452 Views

I am sorry for the late reply.

I am using the fourth option from below for true dual port RAM (as I need all Port A ports to be clocked using one clock and Port B using a different clock)

• Single
• Dual clock: use separate ‘read’
and ‘write’ clocks
• Dual clock: use separate ‘input’
and ‘output’ clocks
• Customize clocks for A and B
ports

What I see is, a lot of ALMs is consumed for FIFO logic (60K ALM) in Agilex. I suppose this is due to the emulated TDP clock mode, while in Arria 10, TDP dual clock mode is natively supported and doesnt consume any ALM. 

My question is, why is this mode not supported in Agilex. Is there a way I can realize separate clock for Port A and B of true dual port RAM without incurring such heavy ALM penalty.

Regards

AlteraUsr
Beginner
436 Views

Hi,

 

Is there any updates to my query.

 

Regards

Nurina
Employee
424 Views

Hi,


I'm not sure why this RAM takes up a lot of ALMs after migration. Try changing some of the parameters (RAM block type, maximum block depth) and re-generate the RAM IP. Make sure your parameters are correctly set, please refer to Table 24 in this documentation for suggested parameter settings: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/ug-ag-memory.pdf#...


Regards,

Nurina


Nurina
Employee
394 Views

Hi, any updates?


Nurina
Employee
384 Views

Hello,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!

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