Is it possible to inject ECC errors at the SDRAM controller on Cyclone V HPS ? These are enabled in the sdr.dramintr register and the status reflected in sdr.dramsts.
I found examples of injecting errors at the cache level and for components that have their own on-chip RAM buffer areas, but the only example I saw for injecting errors at the SDRAM controller used the process of shorting the physical pins of the third SDRAM part on the eval board to corrupt the ECC.
