Input Clock Rate Selection

[Altera_Forum]

What things should be considered when selecting the input clock rate for FPGAs? 

 Background on this question: Previously I have used a 64MHz clock into CycloneI - IV, Cyclone10 or MAX10. Usually the internal clocks after PLL are 80MHz or 144MHz. On a recent design, some jumper wires had to be added to correct traces for the clock. Less than ideal routing caused loss of PLL lock. It then occurred to me that the clock should be much slower to ease board design. A switch was made to 8MHz, which still allowed for 80MHz and 144MHz internally. The PLL is able to stayed locked with this configuration.  Is selecting the slowest possible clock a good idea?  +This has less problems with poor board design.  +The PLL adjustment resolution is finer - might be useful if a new rate is needed later. -More jitter?

[Altera_Forum]

If your PLL fails due to bad layout with 64 MHz, I won't give a damn for better behavior with 8 or 16 MHz clock. That's because it's mostly the clock edge quality which causes the problems as long as the clock level is halfway correct. Anyway I would suggest a low clock frequency like 8 or 16 MHz, crystal oscillator power consumption and EMI are sufficient reasons. Don't forget an impedance matching series resistor at the oscillator to avoid overshoot and double edges. 

 The clock frequency range doesn't affect PLL resolution and jitter with recent FPGA families, because the input frequency can be divided before the phase detector. PLL jitter is mainly caused by the VCO and several orders of magnitude larger than of a good crystal oscillator.

[Altera_Forum]

I agree the edge rise time is a big concern, but the frequency also matters. The reflections just cause a little ringing on the slow clock, while they can crash into the next edge on a fast clock. 

 Thanks for the help.