Input/Help on project using Arria-V Card, Qsys, PCI-E drvr., DDR3, & Avalon BusMaster

[Altera_Forum]

Hi - I do signal processing systems (samples go in, samples go out). In the past, I had the stimulus generator and checkers on-FPGA, and my Qsys system consisted of the JTAG master and my DUT as Avalon slave, and I operated it from System Console. So that's where my head is at. 

 For my current project, I need to get my stimulus from a large memory, and write the DUT output to a large memory. So I envision a system with a PCI-E Interface, a DDR3 interface, and my DUT. I'm doing this on the Arria V SoC Dev. board, but for now I want to avoid the overhead of firing up the HPS (ARM). I have a problem with the default DMA controller in Qsys because you can't make it loop forever (which is what I will do with my input stimulus). I don't know if there's a better one, but what would make things a lot easier is if I could add an Avalon Bus Master to my design, then it could work like:  (DDR3 is partitioned into two sections - stimulus and results) 1) From PC - use PCI interface to load DDR3, and then enable DUT 2) DUT fetches stimulus from DDR3, and writes results to DDR3. From PC, PCI Interface occasionally polls DUT DONE. 3) When DUT DONE, PC uses PCI interface to read results from DDR3.  So the missing pieces are a System-Console-like driver for the PCI Interface and the Avalon Interface. (or possibly, a better DMA controller). Can any one provide pointers to any of these components?  Any/all advice appreciated - thanks! /j  Update: I found this page http://www.altera.com/support/examples/nios2/exm-avalon-mm.html with Avalon drivers from 2007. I don't know if they work or if there's anything better.... Thanks!