Input decay and state machine deadlock

Altera_Forum · ‎02-21-2011

Hello,

I have an Altera device that gets an input from another board. This input drives a complex state machine. When I remove the power from the other board, the input goes low in a 5ms non-monotonous decay. This causes my state machine to lock up. What I did to get this to work is double flop the input, then feed it into the state machine. Is this a recommended solution?

I have signal tap displaying the state machine register, which in normal operation, shows STATE_1, STATE_2, ... When the deadlock happens, signal tap shows 0 for the state. The case for the state machine handles all of the states and includes a default state.

Thank you for any insight on this.

Altera_Forum · ‎02-21-2011

Yes. The problem occurs when you have inputs to a state machine that are not on the same clock domain as the state transitions. One state transition could see the input as 0 while another state transition could see it as a 1. What you did was correct in synchronizing the input.

And, a link to a possibly relevant thread on safe state machines :

http://www.alteraforum.com/forum/showthread.php?t=4566

Altera_Forum · ‎02-21-2011

One way to prevent floating input is to apply onchip weak pullup.

Note, default states may not be implemented(ignored at synthesis).

Altera_Forum · ‎02-21-2011

kbs972, very interesting post you linked there. I was in the dark as far as the "default" in the case statement. Now I know more.

I did leave out that the input signal is synchronized to a clock sourced by the altera device, and hence I thought I was sampling in the correct domain. However, when power is gone, so is synchronization and I have to cdc it.

kaz, I thought about that, but then I will be powering back the other board since it is not removed, but simply powered off. I will probably do that though, since the other board also has an Altera device (Arria GX) which supports hot-swapping and powering pins while the power is off is ok... according to the documentation at least.

Altera_Forum · ‎02-22-2011

Missing synchronization of asynchronous inputs must generally be expected to cause a state machine to get stuck in illegal states. As already mentioned, the synthesized logic ignores any unused respectively illegal states and thus don't necessarily recover from them.

Besides correct synchronization, which is recommended anyway, "safe" state machine encoding will reliably prevent locking in illegal states. It can be specified per FSM defintion by synthesis attributes:

// Safe State machine in Verilog
reg  my_fsm /* synthesis syn_encoding = "safe" */;

-- VHDL
TYPE STATE_TYPE IS (s_idle, s_sync1, s_sync2, s_sync3, s_data, s_check);
ATTRIBUTE syn_encoding : STRING;
ATTRIBUTE syn_encoding OF STATE_TYPE : TYPE IS "safe";	
SIGNAL state  : STATE_TYPE;

Altera_Forum · ‎02-22-2011

FvM, as an experiment, I will remove the double floping of the input (since the lack of it guarantees a dedlock) and make the state machine safe - I am curious how the state machine recovers.. I will test that and report on the results.

Altera_Forum · ‎02-23-2011

Well, I could not re-produce the deadlock. If I get back to this, I will post an update. Thank you guys for the help.