Input pin not found using get_ports command

[Altera_Forum]

Hello All, 

 Here is my problem. I am trying to constrain one of my input clock ports (pll_1705_mclk) for timing analysis using Timequest but when i use the "get_ports" command i get this error message:   Warning: pll_1705_mclk could not be matched with a port.   I have ensured that this port is an INPUT port, this port is assigned to the AA11 port location within the Pin Planner and I've verifified that i've named the port with the same name. I have also ensured that I have "Created Timing Netlist" before using get_ports within Timequest.    I have attached .txt files of the warning messages i recieve during full compilation and timing analyzing.   Any help woudl be great! Thanks everyone.

[Altera_Forum]

If I were to take a guess, your design is getting synthesized away: 

Info: 5394 registers lost all their fanouts during netlist optimizations. The first 100 are displayed below.  If you look in the fitter report, how many registers are there?

[Altera_Forum]

I've run the fitter and under Resource Usage Summary I am seeing the following information: 

 Total registers: 77 / 34,134 (<1%) Dedicated logic registers: 77 / 33,216 (<1%) I/O registers: 0 / 918 (0%)   My apologies, I am new to Quartus II, is this the information you were looking for? I have also attached the warnings and messages I recieved while running the fitter.

[Altera_Forum]

Does 77 seem right? 

One of two things is happening, either the pin doesn't exist(TQ is case-sensitive, so make sure you have that correct). I'm guessing you're sure about the pin name, so the other option is that it got synthesized out. Go to the Technology View and find that input and see if it feeds the clock ports of registers. If it does, it should work.

[Altera_Forum]

Please elaborate on what you mean when you say "synthesized out". How would someone go about resolving that type of problem?  

 The capitalization on the pin name matches what I've used.

[Altera_Forum]

Synthesis always tries to optimize logic. The most common examples are when your logic doesn't drive an output, then all the upstream logic gets synthesized away. Another example is if you forget to hook up an input(on designs with hierarchy, where you instantiate something but don't drive all the inputs), then the downstream logic can get synthesized away. It can be a lot more complicated than that. A large case statement might have conditions that will never evaluate to true, though you think they will, and hence that state and anything based on it gets removed. Start going through the messages and synthesis reports.

[Altera_Forum]

Hello Rysc, 

 I was able to solve the problem using your advice. You were right. I did not have an output pin connected to my logic causing registers to be synthesized away. Thanks for all the help!