Inquiry Regarding Cyclone V IBIS Model Definitions and Updates

[RyusukeYOKOYA]

Dear Intel Support Team,

I hope this message finds you well.

I am currently conducting IBIS simulations for the Cyclone V FPGA, specifically for the part number 5CGXFC9C6F23, and I have a few questions regarding the IBIS model definitions provided on your official website.

Upon reviewing the IBIS file available at the following link:
https://www.intel.co.jp/content/www/jp/ja/support/programmable/support-resources/board-layout/ibs-ibis-index.html
I noticed that several I/O buffer models appear to have identical definitions despite having different names. For example:

• "lvcmos_rtpio_d2s1" and "lvcmos_rtpio_d16s1"
• "lvcmos_rtpio_d2s1_p" and "lvcmos_rtpio_d16s1_p"

These models seem to be completely identical in terms of their IBIS definitions, which raises concerns about their accuracy and applicability for simulation purposes.

I would like to ask the following:

1. Are there any updated or revised IBIS model files for Cyclone V released after March 20, 2020, which is the last modification date shown on the website?
2. Among the available models, which ones are considered accurate and appropriate for simulation, particularly for the I/O standards listed below?

The I/O standards I plan to use are:

• 3.3V LVCMOS (lvcmos_*)
• 3.3V LVTTL (lvttl_*)
• SSTL-135 (sstl135_*)
• Differential SSTL-135 (dsstl135_*)

Your guidance on this matter would be greatly appreciated, as it will help ensure the validity of our signal integrity simulations.

Thank you very much for your support.

Best regards,
Ryusuke YOKOYA

[Farabi]

Hello,

I am taking over this case from previous owner.

You may refer to IBIS user guide downloaded from : https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html

(inside the .zip file)

the xx_p suffix is with clamp diode.

Cyclone V is legacy device. There is no update since March 2020 of the IBIS model.

regards,

Farabi

[RyusukeYOKOYA]

Dear Farabi,

Thank you for your response and for taking over the case.

I would like to clarify a mistake in my initial message. The model pairs I intended to refer to were not:

• "lvcmos_rtpio_d2s1" and "lvcmos_rtpio_d16s1"
• "lvcmos_rtpio_d2s1_p" and "lvcmos_rtpio_d16s1_p"

but rather:

• "lvcmos_rtpio_d2s1" and "lvttl_rtpio_d16s1"
• "lvcmos_rtpio_d2s1_p" and "lvttl_rtpio_d16s1_p"

Upon inspecting the cyclone5.ibs file, I found that these pairs have identical IBIS definitions, despite differing in name, I/O standard, and drive strength. This raises concerns about whether the models are correctly differentiated and whether they can be reliably used for signal integrity simulations.

As FvM pointed out in another thread(Re: Inquiry Regarding Cyclone V IBIS Model Definitions and Updates - Intel Community), the I/V curves of "lvcmos_rtpio_d2s1" do not match the expected behavior for 2 mA drive strength, and instead resemble higher current settings. This suggests that there may be inconsistencies or errors in the IBIS model definitions.

Could you please confirm whether this duplication is intentional, and if not, whether corrected IBIS models are available?

Thank you again for your support.

Best regards,
Ryusuke YOKOYA