Instantiating a black box in Quartus 2 Version 11

[Altera_Forum]

Hi all, 

 I want to instantiate an entity as a black block (A friend will give me the VHDL description of this entity at a later stage) so that I can synthesize the part I have written. I am using Quartus 11 web edition on linux since this is the last version that supports the Cyclone family of FPGA's.  I have declared this entity as a component and added "library altera; use altera.altera_syn_attributes.all;" and "attribute black_box : boolean;attribute black_box of other_comp : component is true;".  if I do not declare an entity description of the other_comp the synthesis process fails because "error: node instance "ua_t" instantiates undefined entity "other_comp".  If I declare the entity and an empty architecture than Altera assumes that the output signals are held at a constant level and minimizes the circuit accordingly.  What do I need to do to generate the "other-comp" as a black box and Altera does not assume that the output signals are a constant logic level.  Thanks,  Regards,  jozamm

[Altera_Forum]

Quartus is trying to synthesis logics. What do you want it to synthesize if not outputting constant level, given an empty box? The is no unknown (X) in real logics, it has to be either 0 or 1. 

 If want you mean is to retain unused logics, I don't understand why you want to do so. For example. an AND gate. If one input is at constant 0, the gate can be removed with output node driven 0 all time. Why would you want to retain the AND?

[Altera_Forum]

Try the attribute syn_black_box instead of black_box. 

 to tzestan: black_boxes can be useful for exactly the OPs setup - synthesising a partial design to test resource usage, or design implementation. He's not trying to put it on an FPGA yet. Black boxes are often needed if a component comes from a netlist, not source code.

[Altera_Forum]

--- Quote Start ---  Try the attribute syn_black_box instead of black_box.  to tzestan: black_boxes can be useful for exactly the OPs setup - synthesising a partial design to test resource usage, or design implementation. He's not trying to put it on an FPGA yet. Black boxes are often needed if a component comes from a netlist, not source code.  --- Quote End ---    Got it. Thanks.

[Altera_Forum]

--- Quote Start ---  Got it. Thanks.  --- Quote End ---    Hi all,  Thanks for your help. Seems that one needs to use the "syn_black_box" attribute but this is not defined in Quartus 11.0  Thanks the same,  Regards,  jozamm

[Altera_Forum]

you can define it youself. You dont need to include altera_syn_attributes package.