Intel Arria10 GX Development Kit - DDR3 example design - traffic_gen_fail

[ats52]

Hello.

I'd like to ask a question about DDR3 example design for Intel Arria 10 GX Development Kit (DK-DEV-10AX115S-A).

I'm facing at the traffic generator test failure (traffic_gen_fail = 1) after getting the calibration success (local_cal_success = 1).

The conditions are followings:

Tool and device:

• Quartus Prime Pro 22.4
• Arria 10 GX Development Kit (DK-DEV-10AX115S-A)
• DDR3 HILO module bundled with Development Kit
• Board Test System (bts_ddr3.sof) passed with no errors

DDR3 IP

• External Memory Interfaces Intel Arria 10 FPGA IP (DDR3)
• Applied the preset for DDR3 HILO for Arria 10 GX Development Kit
• No additional modification applied to the IP configuration
• Generate Example Design

Example Design

• LED D3 Green (local_cal_success), LED D10 Red (traffic_gen_fail) are ON
• The simulation provided with the example design passes, thus it reaches both local_cal_success and traffic_gen_pass asserted.
• With Signal Tap, address and writedata matches the simulation result, on the other hand, readdata looks unmached from the first data when the traffic generator test started.
• With External Memory Interface Toolkit, the calibration report looks fine.
• If DDR3 IP configured with Efficiency Monitor Interface, it shows 89.04%, the other reports look fine to me.

Others

• I have tested with several Arria 10 GX Development Kit boards, however, they shows same symptom.

I'll appreciate if any information to solve this situation.

[AdzimZM_Intel]

Hi ats52,

Are you using the bts design with version v15.1.2? (arria10GX_10ax115sf45_fpga_v15.1.2)

If yes, the row address width is set to 16 and RZQ pin is assigned in Bank 2J in this design.

I will share the example design later. Please test the design and check for the status (LED).

Regards,

Adzim

[AdzimZM_Intel]

Please test this example design and let me know the status.

[ats52]

Hello AdzimZM

Great thanks for your quick reply.

Are you using the bts design with version v15.1.2? (arria10GX_10ax115sf45_fpga_v15.1.2)

No,  I'm using arria10GX_10ax115sf45_fpga_v22.4.0_v1.1.zip for BTS, which can be downloaded from this link.

https://cdrdv2.intel.com/v1/dl/getContent/649761

If you let me know the link for arria10GX_10ax115sf45_fpga_v15.1.2, I'm willing to test it as well.

For the example design you kindly sent,  I have confirmed many parameters are updated from mine especially in ip/ed_synth/ed_synth_tg.ip, however, the LEDs show the same error status, thus local_cal_success and traffic_gen_fail.

I have following confirmations:

• If I suppose you have an Arria 10 GX Development Kit board, the project I attached works fine on your board?
• As far as I've looked into the installer package of arria10GX_10ax115sf45_fpga_v22.4.0_v1.1.zip, it looks only SOF files are included for BTS items, the project designs are not. Is it possible to get the project design for BTS of DDR3? Since BTS and the example design test for DDR3 make difference, I hope I will be able to find some clues if the project is available.

Thanks in advance for your reply.

Best regards,

[AdzimZM_Intel]

Hi ats52,

"If I suppose you have an Arria 10 GX Development Kit board, the project I attached works fine on your board?"

• Currently we have some hardware limitation to test the design. Thus, I cannot test the design you provided.

"As far as I've looked into the installer package of arria10GX_10ax115sf45_fpga_v22.4.0_v1.1.zip, it looks only SOF files are included for BTS items, the project designs are not. Is it possible to get the project design for BTS of DDR3? Since BTS and the example design test for DDR3 make difference, I hope I will be able to find some clues if the project is available"

• You can use the design from "arria10GX_10ax115sf45_fpga_v22.4.0_v1.1.zip\arria10GX_10ax115sf45_fpga_v22.4.0_v1.1\examples\memory\PRD\qts_ddr3_x72_1066MHz" to run the test.
• I think it's similar to BTS design.

Regards,

Adzim

[ats52]

Hi AdzimZM

Thanks for the information about the BTS design. Indeed it is there in the archive.

I have compared the EMIF IP configuration between the generated example design and the DUT in BTS.
There are not that many parameters different from each other, however they does make difference.

I have applied to the following configuration parameters of BTS to the EMIF DDR3 IP in the example design, in addition to the design itself differences (address width, ECC enable/disable) etc.

Tab	sub category	parameter name	emif_0 (example design)	ed_synth_dut_0 (board support test)
Mem I/O	Memory I/O Settings	ODT Rtt nominal value	ODT Disabled	RZQ/2
-	-	Dynamic ODT (Rtt_WR) value	RZQ/4	Dynamic ODT off
FPGA I/O	Address/Command	Output mode	12 mA	8 mA
-	-	Slew rate	unset	Fast
-	Memory Clock	Output mode	12 mA	8 mA
-	-	Slew rate	unset	Fast
Mem Timing	Parameters dependent on Speed Bin, Operating Frequency, and Page Size	tRRD	6	7
-	-	tFAW	25.0	35.0
-	Parameters dependent on Density and Temperature	tRFC	160.0	260.0

Now I got the successful result with both local_cal_success and traffic_gen_pass.

Thank you for your support.

Best regards,

[AdzimZM_Intel]

Hi ats52,

I'm glad that now your issue is resolved. I hope you can continue further to finish your design or project with successful result.

I now transition this thread to community support.

If you have a new question, feel free to open a new thread to get the support from Intel experts.

Otherwise, the community users will continue to help you on this thread.

Thank you.

Regards,

Adzim